Senior ASIC Verification Lead, Tape-out Ready

Eridu; Saratoga (CA); Hybrid; USD 180,000 - 280,000; Full time

Job summary

Eridu is seeking a hands-on ASIC Design Verification Lead to own verification strategy for high-performance networking silicon. This senior technical role drives verification infrastructure, coverage, and tape-out readiness while staying hands-on in verification tasks.

The ideal candidate has deep SystemVerilog and UVM expertise, with a track record of taking complex ASICs to tape-out in a fast-moving startup. Collaboration across RTL, architecture, and firmware is essential.

Qualifications

• Strong hands-on experience in ASIC design verification.
• Proven track record of taking at least one complex ASIC to tape-out with direct verification ownership.
• Deep expertise in SystemVerilog and UVM-based verification methodologies.
• Strong understanding of ASIC design and verification flows, including simulation, coverage, and debug.
• Experience with block-level through full-chip verification and integration.
• Ability to drive execution in ambiguous, fast-paced startup environments.
• Excellent communication skills and ability to collaborate across disciplines.

Responsibilities

• Define and own block-, subsystem-, and chip-level verification strategies
• Develop and maintain scalable verification environments using SystemVerilog and UVM
• Drive execution from test-plan definition through coverage and bug closure
• Ensure verification readiness as a gating requirement for tape-out
• Write and review high-quality testbenches, sequences, checkers, and scoreboards
• Develop constrained-random, directed, and stress tests to validate complex corner cases
• Actively debug functional failures across RTL, testbench, and simulation environments

Skills

ASIC verification

SystemVerilog

UVM

Tape-out experience

Cross-functional collaboration

Tools

SystemVerilog

UVM

Job description

Eridu is seeking a hands-on ASIC Design Verification Lead to own verification strategy for high-performance networking silicon. This senior technical role drives verification infrastructure, coverage, and tape-out readiness while staying hands-on in verification tasks.

The ideal candidate has deep SystemVerilog and UVM expertise, with a track record of taking complex ASICs to tape-out in a fast-moving startup. Collaboration across RTL, architecture, and firmware is essential.