Senior ASIC Verification Lead for Networking

Eridu Corporation; Saratoga (CA); On-site; USD 190,000 - 270,000; Full time

Job summary

Eridu is seeking a hands-on ASIC Design Verification Lead to own verification strategy, infrastructure, and closure for high-performance networking silicon. This senior role requires deep expertise and practical hands-on work beyond management in a fast-moving startup.

You will define verification plans, develop scalable environments, and drive coverage goals while collaborating with RTL, physical design, and firmware teams to ensure tape-out readiness.

Qualifications

• Strong hands-on experience in ASIC design verification.
• Proven track record of taking at least one complex ASIC to tape-out with direct verification ownership.
• Deep expertise in SystemVerilog and UVM-based verification methodologies.
• Strong understanding of ASIC design and verification flows, including simulation, coverage, and debug.

Responsibilities

• Define and own block-, subsystem-, and chip-level verification strategies.
• Develop and maintain scalable verification environments using SystemVerilog and UVM.
• Drive execution from test-plan definition through coverage and bug closure.
• Ensure verification readiness as a gating requirement for tape-out.
• Write and review high-quality testbenches, sequences, checkers, and scoreboards.
• Develop constrained-random, directed, and stress tests to validate complex corner cases.
• Actively debug functional failures across RTL, testbench, and simulation environments.

Skills

ASIC verification

SystemVerilog

UVM

Tape-out ownership

Debugging

Tools

SystemVerilog

UVM

Job description

Eridu is seeking a hands-on ASIC Design Verification Lead to own verification strategy, infrastructure, and closure for high-performance networking silicon. This senior role requires deep expertise and practical hands-on work beyond management in a fast-moving startup.

You will define verification plans, develop scalable environments, and drive coverage goals while collaborating with RTL, physical design, and firmware teams to ensure tape-out readiness.