ASIC Design Verification Lead

Eridu Corporation; Saratoga (CA); On-site; USD 190,000 - 270,000; Full time

Job summary

Eridu is seeking a hands-on ASIC Design Verification Lead to own verification strategy, infrastructure, and closure for high-performance networking silicon. This senior role requires deep expertise and practical hands-on work beyond management in a fast-moving startup.

You will define verification plans, develop scalable environments, and drive coverage goals while collaborating with RTL, physical design, and firmware teams to ensure tape-out readiness.

Qualifications

• Strong hands-on experience in ASIC design verification.
• Proven track record of taking at least one complex ASIC to tape-out with direct verification ownership.
• Deep expertise in SystemVerilog and UVM-based verification methodologies.
• Strong understanding of ASIC design and verification flows, including simulation, coverage, and debug.

Responsibilities

• Define and own block-, subsystem-, and chip-level verification strategies.
• Develop and maintain scalable verification environments using SystemVerilog and UVM.
• Drive execution from test-plan definition through coverage and bug closure.
• Ensure verification readiness as a gating requirement for tape-out.
• Write and review high-quality testbenches, sequences, checkers, and scoreboards.
• Develop constrained-random, directed, and stress tests to validate complex corner cases.
• Actively debug functional failures across RTL, testbench, and simulation environments.

Skills

ASIC verification

SystemVerilog

UVM

Tape-out ownership

Debugging

Tools

SystemVerilog

UVM

Job description

About this position

About Eridu

Eridu is a Silicon Valley-based hardware startup pioneering infrastructure solutions that accelerate AI data centers to deliver Faster AI . Today’s AI performance is frequently limited by communication bottlenecks. Eridu delivers multiple industry-first innovations across silicon, packaging, software, and systems to deliver a step function in AI networking – a network switch that is an order of magnitude improvement in bandwidth and radix versus today’s “state of the art” switches. This is the first silicon and system designed from the ground up for AI and the increase in radix and throughput unlocks greater GPU utilization to speed training job completion times and tokens-per-second for more profitable inference. We do this while simultaneously reducing capital and power costs, improving reliability, simplifying operations and speeding AI data center deployments for faster time to revenue.

The company’s solutions and value proposition have been widely validated by leading hyperscalers.

The company has raised $200M to date including its most recent, oversubscribed Series A round led by Socratic Partners, John Doerr, Hudson River Trading, Capricorn Investment Group and Matter Venture Partners, with participation by SBVA, MediaTek, Bosch Ventures, TDK Ventures, Eclipse Ventures, and VentureTech Alliance, among others.

Eridu is led by a veteran team of Silicon Valley executives who have delivered multiple billion dollar product lines and led multiple companies to billion dollar exits, including serial entrepreneur Drew Perkins, co-founder of Infinera (NASDAQ: INFN), Lightera (acq. by Ciena), Gainspeed (acq. by Nokia) and Mojo Vision (the world’s leading micro-LED company). The company is in execution mode and has a world-class engineering team with decades of experience in state-of-the‑art silicon, packaging, optics, software, and systems. Eridu has also assembled a world class IP, design and manufacturing ecosystem to execute on its vision, and counts TSMC as a key partner in our journey.

Visit our website eridu.ai to learn more.

Position Overview

We are seeking a hands-on ASIC Design Verification Lead to own verification execution for complex, high-performance networking silicon. This role is a senior technical leadership position focused on driving verification strategy, infrastructure, and closure, while remaining deeply involved in day-to-day hands-on verification work.

This is not a people-manager-only role. The ideal candidate is a highly technical verification leader who has personally taken chips to tape-out, understands how verification breaks late in the cycle, and can drive functional correctness, coverage closure, and tape-out readiness in a fast-moving startup environment.

Responsibilities

• Define and own block-, subsystem-, and chip-level verification strategies
• Develop and maintain scalable verification environments using SystemVerilog and UVM
• Drive execution from test-plan definition through coverage and bug closure
• Ensure verification readiness as a gating requirement for tape-out
• Write and review high-quality testbenches, sequences, checkers, and scoreboards
• Develop constrained-random, directed, and stress tests to validate complex corner cases
• Actively debug functional failures across RTL, testbench, and simulation environments

Coverage & Quality Ownership

• Define functional, code, and assertion coverage goals
• Analyze coverage results and identify verification gaps
• Provide clear, actionable feedback to RTL designers to improve design and test quality

Cross-Functional Debug & Collaboration

• Partner closely with RTL, architecture, physical design, and firmware teams
• Drive root-cause analysis of functional, performance, and integration issues
• Support gate-level, timing-aware, and power-aware simulations as required
• Partner and support emulation and post silicon validation of the ASIC design
• Lead full-chip verification planning, execution, and closure
• Support emulation and acceleration environments where appropriate
• Ensure clean handoff to silicon bring-up teams with high confidence in design correctness

Execution Discipline & Technical Leadership

• Establish and enforce verification checklists and quality gates
• Track verification progress and risk, proactively escalating issues
• Lead by technical authority and hands-on contribution rather than coordinate alone
• Continuously improve verification methodology, infrastructure, and best practices

Qualifications

• Strong hands-on experience in ASIC design verification
• Proven track record of taking at least one complex ASIC to tape-out with direct verification ownership
• Deep expertise in SystemVerilog and UVM-based verification methodologies
• Strong understanding of ASIC design and verification flows, including simulation, coverage, and debug
• Experience with block-level through full-chip verification and integration
• Ability to drive execution in ambiguous, fast-paced startup environments
• Excellent communication skills and ability to collaborate across disciplines

Nice to Have

• Networking ASIC verification experience (Ethernet-based systems preferred)
• Experience with gate-level, timing-aware, and low-power verification
• Familiarity with high-speed interfaces and chip-to-chip interconnects
• Experience with emulation, acceleration, or FPGA-based validation
• Post-silicon debug experience and RTL-to-silicon correlation

Why Join Us?

At Eridu, you’ll have the opportunity to shape the future of AI infrastructure, working with a world-class team on groundbreaking technology that pushes the boundaries of AI performance. Your contributions will directly impact the next generation of AI infrastructure solutions, transforming the performance of AI data centers.

The starting base salary for the selected candidate will be established based on their relevant skills, experience, qualifications, work location, market trends, and the compensation of employees in comparable roles.

Notice to Recruiting Agencies

Eridu does not accept unsolicited resumes or candidate profiles from staffing agencies or third-party recruiters. Any candidate submitted to Eridu without prior written authorization from our recruiting team will be considered unsolicited and will become the property of Eridu. Eridu reserves the right to pursue and hire such candidates without any obligation to pay fees. Recruiting agencies are expressly instructed not to contact hiring managers, employees, or executives regarding open positions.

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