IC Verification Engineer – SystemVerilog, UVM + Equity

Broadcom Inc.; San Jose (CA); On-site; USD 120,000 - 192,000; Full time

Benefits offered by this job

Medical, dental, and vision plans

401(k) with company matching

Employee Stock Purchase Program

Paid time off

Company-paid holidays

Job summary

Broadcom Inc. is seeking a Design Verification Engineer in San Jose, California to create and deliver complex switch design verifications. Responsibilities include developing SystemVerilog-based environments and executing rigorous test plans for RTL and gatesim designs.

The ideal candidate possesses a master's degree in a technical field and at least six years of design verification experience. This role offers a competitive salary and comprehensive benefits package, including health insurance, 401(k), and stock purchase options.

Qualifications

• Master's degree in relevant field required.
• Minimum of six years of experience in Design Verification.
• Strong knowledge of verification methods and tools.

Responsibilities

• Create SystemVerilog-based verification environments.
• Develop and execute test plans for verification.
• Create ATE testing vectors and C-based diagnostic tests.

Skills

Verification methods

SystemVerilog programming

Scripting languages

UVM methodology

Networking concepts

Education

Master's degree in Electrical and Electronic Engineering or Computer Science

Job description

Broadcom Inc. is seeking a Design Verification Engineer in San Jose, California to create and deliver complex switch design verifications. Responsibilities include developing SystemVerilog-based environments and executing rigorous test plans for RTL and gatesim designs.

The ideal candidate possesses a master's degree in a technical field and at least six years of design verification experience. This role offers a competitive salary and comprehensive benefits package, including health insurance, 401(k), and stock purchase options.