Senior ASIC Verification Engineer | SoC/UVM + Equity

NVIDIA AI; Santa Clara (CA); On-site; USD 136,000 - 265,000; Full time

Job summary

NVIDIA is seeking a senior ASIC DV engineer to define verification strategies at the full‑chip level and collaborate with architects, RTL designers, FPGA and emulation teams.

The role focuses on building and refining verification infrastructure, writing testbenches, and solving complex SoC verification challenges. A Bachelors in EE/CS/CE and 5+ years of ASIC DV experience are required, with equity and benefits offered.

Qualifications

• Bachelor's Degree in EE, CS, CE, or equivalent experience.
• 5+ years of relevant ASIC DV experience.
• Strong analytical and problem-solving skills.
• Experience crafting testbenches and methodologies for large chips.
• Proficiency in C++, OOP, UVM or SystemVerilog.

Responsibilities

• Define verification strategies and plans at full chip level.
• Build and reform verification infrastructure and methodologies.
• Collaborate with architects, RTL designers, FPGA and emulation engineers.

Skills

C++

OOP

UVM

SystemVerilog

Testbenches

Education

Bachelor's in EE/CS/CE

Job description

NVIDIA is seeking a senior ASIC DV engineer to define verification strategies at the full‑chip level and collaborate with architects, RTL designers, FPGA and emulation teams.

The role focuses on building and refining verification infrastructure, writing testbenches, and solving complex SoC verification challenges. A Bachelors in EE/CS/CE and 5+ years of ASIC DV experience are required, with equity and benefits offered.