Senior ASIC Verification Engineer for SoC Excellence

LitePoint; North Reading (MA); On-site; USD 123,000 - 197,000; Full time

Job summary

Teradyne in North Reading, MA is seeking an ASIC Verification Engineer to develop and verify complex ASIC/SoC designs that power Teradyne’s test technology.

You will join the ASIC Reference Model team, building SystemC and SystemVerilog/UVM environments, collaborating across design, firmware, software, and validation to ensure broad feature coverage. This senior role emphasizes strategic verification, debug, and delivering high-quality results on schedule, with a discretionary bonus program.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related technical field
• 4+ years of ASIC/SoC verification experience in semiconductor product development
• Experience with SystemC and C++
• Object Oriented Programming experience
• Experience developing verification environments using SystemVerilog and UVM
• Deep understanding of functional verification methodologies, constrained-random verification, and coverage closure
• Experience with assertion-based verification and scripting using Python, Perl, or similar languages
• Knowledge of industry-standard EDA simulation and debug tools
• Experience verifying complex digital designs, interconnects, memory subsystems, and high-speed interfaces
• Strong analytical and problem-solving skills with the ability to debug complex functional issues
• Excellent collaboration and communication skills in a cross-functional engineering environment
• Preferred experience with formal verification methodologies
• Preferred experience supporting silicon bring-up and post-silicon validation activities

Responsibilities

• Verification planning, testbench architecture, and execution for complex ASIC and SoC designs
• Develop and maintain SystemC and SystemVerilog/UVM reference models
• Develop and maintain SystemVerilog/UVM-based verification environments, test cases, and reusable verification components
• Collaborate closely with design, architecture, firmware, software, and validation teams to ensure comprehensive feature coverage
• Build and execute verification strategies utilizing simulation, coverage-driven verification, assertions, and formal methodologies
• Support debug and root-cause analysis of functional issues identified during verification and silicon bring-up activities
• Partner with cross-functional teams to define verification requirements, milestones, and quality metrics
• Ensure verification deliverables are completed with high quality, on schedule, and aligned with project objectives

Skills

SystemC

C++

OOP

Python

Education

Bachelor's in EE/CE/CS

Master's preferred

Tools

SystemVerilog

UVM

EDA tools

Python scripting

Job description

Teradyne in North Reading, MA is seeking an ASIC Verification Engineer to develop and verify complex ASIC/SoC designs that power Teradyne’s test technology.

You will join the ASIC Reference Model team, building SystemC and SystemVerilog/UVM environments, collaborating across design, firmware, software, and validation to ensure broad feature coverage. This senior role emphasizes strategic verification, debug, and delivering high-quality results on schedule, with a discretionary bonus program.