Senior ASIC Verification Architect — AI/ML TPU Hardware

Google Inc.; Sunnyvale (CA); On-site; USD 156,000 - 229,000; Full time

Job summary

A leading tech company in Sunnyvale, CA, is seeking a Mid-level Design Verification Engineer. In this role, you will shape cutting-edge TPU technology for AI/ML applications. You will be responsible for verifying complex digital designs, collaborating with design teams, and utilizing your expertise in SystemVerilog and UVM. The position requires at least 8 years of experience in design verification and offers a competitive salary range of $156,000-$229,000 plus bonuses and benefits.

Qualifications

• 8 years of experience with design verification.
• Experience with the full verification life cycle.
• Experience with three or more SoC projects.

Responsibilities

• Plan the verification of complex digital design blocks.
• Create and enhance constrained-random verification environments.
• Identify and write coverage measures for stimulus and corner-cases.

Skills

Design verification

SystemVerilog

UVM

Education

Bachelor's degree in Electrical Engineering, Computer Engineering, or related field

Master's degree or PhD in relevant field

Tools

Industry standard tools for silicon-based ICs

Job description

A leading tech company in Sunnyvale, CA, is seeking a Mid-level Design Verification Engineer. In this role, you will shape cutting-edge TPU technology for AI/ML applications. You will be responsible for verifying complex digital designs, collaborating with design teams, and utilizing your expertise in SystemVerilog and UVM. The position requires at least 8 years of experience in design verification and offers a competitive salary range of $156,000-$229,000 plus bonuses and benefits.