Senior ASIC/SoC Design Architect | RTL & Verification

Cypress HCM; Brooklyn Park (MN); On-site; USD 150,000 - 205,000; Full time

Job summary

Cypress HCM in Minnesota is seeking an experienced ASIC Chip Design Lead to guide the full chip development lifecycle from architecture to verification.

This hands-on leadership role requires deep RTL expertise, collaboration with system teams, and mentoring of engineers in a distributed environment. Candidates should have 10+ years in ASIC/SoC design, strong Verilog/SystemVerilog skills, and proficiency with Linux/Unix and scripting.

Qualifications

• 10+ years of ASIC/SoC design experience.
• Proficiency in RTL-based digital IC design using Verilog/SystemVerilog.
• Experience across multiple stages of the ASIC/SoC development flow.
• Strong scripting ability and Linux/UNIX proficiency.

Responsibilities

• Lead ASIC/SoC architecture and development based on system requirements.
• Define functionality, interfaces, specifications, and performance goals with teams.
• Design and implement complex digital blocks in Verilog/SystemVerilog.
• Develop and optimize RTL for power, performance, and area.
• Perform synthesis and analyze results with EDA tools.
• Develop timing constraints and support timing closure.
• Collaborate with physical design on floorplanning, placement, routing, and design closure.
• Support processor integration, constraint development, and performance optimization.
• Work with verification engineers for functional correctness.
• Contribute to design methodology improvements and best practices.
• Mentor engineers and provide technical leadership.

Skills

RTL design

Verilog/SystemVerilog

ASIC/SoC design

Scripting (Python/Tcl)

Linux/UNIX

Mentoring/leadership

Education

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science

Tools

EDA tools

Job description

Cypress HCM in Minnesota is seeking an experienced ASIC Chip Design Lead to guide the full chip development lifecycle from architecture to verification.

This hands-on leadership role requires deep RTL expertise, collaboration with system teams, and mentoring of engineers in a distributed environment. Candidates should have 10+ years in ASIC/SoC design, strong Verilog/SystemVerilog skills, and proficiency with Linux/Unix and scripting.