Senior ASIC RTL Architect — PPA Leader + Equity

Positron Corporation; Austin (TX); On-site; USD 200,000 - 300,000; Full time

Job summary

Positron AI is seeking a Senior ASIC Design Engineer to lead the microarchitecture, RTL development, and signoff for cutting‑edge inference accelerators. You will own critical IP blocks, guide verification and PD teams, and drive PPA improvements while mentoring junior engineers.

The role emphasizes hands‑on SystemVerilog design, architectural tradeoffs, and collaboration with architecture, verification, and performance teams to deliver silicon that meets ambitious targets.

Qualifications

• BS/MS in EE/CE (or related) with 8+ years of ASIC/SoC RTL design experience on complex, high‑performance silicon.
• Proven track record of leading designs from spec → microarchitecture → RTL → signoff with strong PPA outcomes.
• Deep SystemVerilog RTL expertise, including clocking, resets, CDC/RDC handling, and protocol correctness.
• Extensive experience with front‑end flows/tools (lint, CDC, synthesis/STA, DFT) using major EDA suites.
• Hands‑on expertise with at least three of: HBM/DDR, PCIe/CXL, AMBA AXI/ACE/CHI, cache/memory hierarchies, high‑throughput datapaths.
• Strong cross‑functional communication skills, capable of leading technical discussions and producing clear specifications.

Responsibilities

• Define and document microarchitecture for complex IP blocks/subsystems.
• Deliver production‑quality, parameterized SystemVerilog RTL with well‑defined interfaces, power/clock intent, and embedded assertions.
• Lead lint, CDC/RDC, DFT integration, and synthesis bring‑up; collaborate with PD on floorplan and timing closure.
• Own PPA metrics for assigned blocks and drive microarchitectural optimizations to meet targets.
• Architect and integrate high‑performance interconnects (AXI/CHI/ACE), DMA engines, coherency logic, and high‑speed memory interfaces (HBM/DDR).
• Engage with IP vendors and internal stakeholders to ensure seamless integration.
• Develop and enforce coding guidelines, reusable IP packaging, and signoff checklists.
• Contribute automation flows (Python/Tcl/Make/CI) to improve team efficiency.
• Partner closely with Verification to define test plans and reference models.
• Work with Architecture and Performance teams to correlate models against RTL.
• Support bring‑up, post‑silicon debug, and customer engagements as required.
• Guide junior engineers in design techniques, methodology, and problem‑solving.
• Lead design reviews, drive consensus on tradeoffs, and advocate for best‑in‑class solutions.

Skills

SystemVerilog

RTL design

PPA optimization

Cross-functional leadership

Mentorship

Education

BS/MS EE/CE

Tools

EDA tool suites

Job description

Positron AI is seeking a Senior ASIC Design Engineer to lead the microarchitecture, RTL development, and signoff for cutting‑edge inference accelerators. You will own critical IP blocks, guide verification and PD teams, and drive PPA improvements while mentoring junior engineers.

The role emphasizes hands‑on SystemVerilog design, architectural tradeoffs, and collaboration with architecture, verification, and performance teams to deliver silicon that meets ambitious targets.