Senior ASIC Physical Design Engineer – Space-Grade RF/SWaP

InvestedintheMission; San Francisco (CA); On-site; USD 197,529 - 276,539; Full time

Benefits offered by this job

Relocation provided

Travel up to 10% of time

On-site work in multiple locations

Job summary

Blue Origin seeks a Senior Silicon Physical Design and Layout Engineer to design and implement ASICs for space-based communications, handling analog/digital processing, floorplanning, power, clock tree, and radiation-hardened layouts.

You will work with Cadence, Synopsys, and Mentor tools; require 7+ years of experience and a background in mixed-signal/RF design. On-site roles across CA/TX/WA with relocation support.

Qualifications

• 7+ years of experience in physical design and layout of ASICs.
• Demonstrated expertise in digital and analog layout techniques.
• Experience with industry-standard EDA tools for physical design (Cadence, Synopsys, or Mentor).
• Knowledge of semiconductor fabrication processes and design rules.
• Understanding of timing closure and signal integrity challenges.

Responsibilities

• Execute physical design and layout of ASICs that integrate both analog and digital processing.
• Implement floor planning, power distribution, clock tree synthesis, and routing for complex mixed-signal designs.
• Develop ASICs that meet the stringent standards of space qualification, ensuring high performance and efficiency.
• Perform timing closure, signal integrity analysis, and physical verification (DRC/LVS/ERC).
• Implement advanced RF processing technologies that support missions with reduced size, weight, and power (SWaP).
• Optimize layouts for radiation tolerance and reliability in the space environment.
• Collaborate with front-end designers to ensure design intent is preserved through implementation.
• Perform static timing analysis and address timing violations.
• Utilize data analytics to optimize ASIC performance and drive innovation.
• Work with semiconductor foundries to ensure manufacturability and yield optimization.
• Implement design for test (DFT) structures and methodologies.
• Document physical design processes, methodologies, and results.
• Support post-silicon validation and debug activities.

Skills

ASIC physical design

Analog layout

Digital layout

Timing closure

Power analysis

Education

B.S. in Electrical Engineering or related field

Advanced degree (MS/PhD) preferred

Tools

Cadence

Synopsys

Mentor

Job description

Blue Origin seeks a Senior Silicon Physical Design and Layout Engineer to design and implement ASICs for space-based communications, handling analog/digital processing, floorplanning, power, clock tree, and radiation-hardened layouts.

You will work with Cadence, Synopsys, and Mentor tools; require 7+ years of experience and a background in mixed-signal/RF design. On-site roles across CA/TX/WA with relocation support.