Senior ASIC Performance Architect & Modeling

Meta; Salem (OR); On-site; USD 178,000 - 250,000; Full time

Job summary

Meta's Silicon Engineering organization is building custom silicon solutions that power the infrastructure underpinning Meta's AI and data center workloads at scale. As an ASIC Engineer specializing in performance and modeling, you will define and drive the architectural performance analysis, pre-silicon modeling, and microarchitectural exploration of custom ASICs designed for Meta's infrastructure.

In this role, you will establish the performance modeling methodology and long-term silicon

Qualifications

• Bachelor's degree or equivalent practical experience in CS/CE or related field.
• 8+ years in ASIC design, silicon engineering, or related field.
• 5+ years in ASIC performance modeling or pre-silicon simulation.
• Proficiency in C++ and Python for modeling and tooling.
• Experience with cycle-accurate or transaction-level models using C++/SystemC.

Responsibilities

• Define and own the performance modeling strategy for custom ASICs.
• Drive microarchitectural exploration across compute, memory, interconnect, and I/O.
• Develop and validate pre-silicon performance models for data center workloads.
• Collaborate with architecture, RTL, and physical design teams to implement specs.
• Lead reviews and communicate results to engineering leadership.
• Mentor engineers in performance modeling and analysis best practices.

Skills

C++

Python

SystemC

Performance modeling

Microarchitectural analysis

ASIC design

Pre-silicon simulation

Data center workloads

Education

Bachelor's degree in Computer Science/Engineering or related field

Tools

SystemVerilog

VHDL

RTL design tools

Job description

Meta's Silicon Engineering organization is building custom silicon solutions that power the infrastructure underpinning Meta's AI and data center workloads at scale. As an ASIC Engineer specializing in performance and modeling, you will define and drive the architectural performance analysis, pre-silicon modeling, and microarchitectural exploration of custom ASICs designed for Meta's infrastructure.

In this role, you will establish the performance modeling methodology and long-term silicon