Senior ASIC Methodology Engineer for ML Accelerators

Amazon; Austin (TX); On-site; USD 185,000 - 250,000; Full time

Benefits offered by this job

Health insurance

401(k) matching

Paid time off

Parental leave

RSUs

Job summary

Annapurna Labs, an organization within Amazon, is seeking an ASIC Physical Design Methodology Engineer in Austin, TX to advance hardware design for ML accelerator chips. You will develop RTL2GDS flows, optimize CAD toolchains, and work with RTL, Physical, and Package teams to improve QoR and design reliability.

The role requires strong scripting abilities (Python/TCL) and extensive experience in ASIC, digital design, and post-silicon verification.

Qualifications

• 7+ years ASIC implementation, synthesis, STA and physical design in deep sub-micron nodes.
• 7+ years of digital design in communication systems.
• 7+ years of full-custom analog or RF layout experience.
• Experience with post-silicon flow automation and verification.
• Bachelor's degree in Electrical Engineering or related field.

Responsibilities

• Define, develop and deploy physical design and verification methodologies for ML accelerator chips.
• Drive CAD flow optimizations for PPA and timing targets.
• Collaborate with RTL, Physical, and Package Design teams to improve flows.
• Create dashboards and reports for project tracking and QoR metrics.
• Interface with EDA vendors and troubleshoot tool flows independently.

Skills

ASIC implementation

Digital design

Python scripting

UVM

C programming

SystemC

RTL2GDS

Scripting (TCL)

CAD flow optimization

Education

Bachelor's degree in Electrical Engineering

Master's/PhD preferred

Tools

MATLAB

Python

C++

EDA tools

SystemC

Job description

Annapurna Labs, an organization within Amazon, is seeking an ASIC Physical Design Methodology Engineer in Austin, TX to advance hardware design for ML accelerator chips. You will develop RTL2GDS flows, optimize CAD toolchains, and work with RTL, Physical, and Package teams to improve QoR and design reliability.

The role requires strong scripting abilities (Python/TCL) and extensive experience in ASIC, digital design, and post-silicon verification.