Senior ASIC Design Infrastructure & Methodologies engineer, MLA-MI – Annapurna Labs

Anysilicon; Austin (TX); Hybrid; USD 180,000 - 250,000; Full time

Job summary

Amazon is seeking an ASIC Design Methodologies and Infrastructure Engineer to advance automation and design flows for AI workloads. You will work with architects, designers, and verification engineers to refine processes and deploy scalable infrastructure across the silicon development lifecycle.

Responsibilities include creating and implementing new design methodologies, improving flow productivity, and collaborating with vendors on tool evaluation and qualification to keep our silicon

Qualifications

• 7+ years of ASIC implementation, synthesis, STA, and physical design in 16nm or smaller.
• 7+ years of digital design in communication systems.
• 8+ years of creating and maintaining automation frameworks for Post-Silicon Flow.
• 7+ years of verification in communication systems.
• 5+ years of UVM, C, SystemC, and scripting experience.

Responsibilities

• Develop and implement new methodologies and infrastructure to enhance design team efficiency and quality.
• Enhance and build design flows to improve overall productivity of design teams.
• Collaborate with vendors to evaluate and qualify new design tools and updated tool versions.

Skills

RTL design

Front-end methodologies

Cross-functional collaboration

Automation scripting

Tools

Automation frameworks

Post-Silicon Flow

Job description

Join our Machine Learning Acceleration (MLA) team at Amazon, where we design and develop SOCs that power AI workloads globally. As an ASIC Design Methodologies and Infrastructure Engineer, you will automate design flows and build large-scale solutions to enhance silicon development. This role requires collaboration with architects, designers, and verification engineers to refine design processes and introduce innovative automation solutions.

Responsibilities:

• Develop and implement new methodologies and infrastructure to enhance design team efficiency and quality.
• Enhance and build design flows to improve overall productivity of design teams.
• Collaborate with vendors to evaluate and qualify new design tools and updated tool versions.

Qualifications:

• 7+ years of ASIC implementation, synthesis, STA, and physical design in deep sub-micron nodes (16nm or smaller).
• 7+ years of digital design in communication systems.
• 7+ years of full-custom analog or RF layout experience.
• 7+ years of wireless communications systems and implementation experience.
• 8+ years of creating and maintaining automation frameworks for Post-Silicon Flow.
• 7+ years of verification in communication systems.
• 5+ years of UVM, C, System C, and scripting experience.

Skills:

• Proven expertise in RTL design and front-end methodologies.
• Strong software skills for improving and automating design flows.
• Ability to collaborate effectively with cross-functional teams.

Tell us what you're building and we'll recommend qualified vendors for your project.

• ASIC Design Services
• Verification
• Packaging & Wafer
• Semiconductor IP

Find the Right Semiconductor Partner

Tell us what you're building and we'll recommend qualified vendors for your project.

• ASIC Design Services
• Verification
• Packaging & Wafer
• Semiconductor IP

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