Senior ASIC Front-End Design Engineer — Pre-IPO Stock

Ethernovia; San Jose (CA); Hybrid; USD 200,000 - 300,000; Full time

Benefits offered by this job

Pre IPO stock options

Competitive base salary

Flexible hours

Medical, dental and vision insurance

Job summary

Ethernovia, Inc. is seeking a Senior ASIC Front-End Design Engineer in San Jose, CA on a hybrid schedule. You will own RTL design, verification, and timing for automotive SoCs, collaborating with system architects and cross-functional teams to deliver high-performance, power-efficient ASICs.

A self-driven leader with 10+ years in ASIC RTL is ideal for this role. You’ll work with Verilog/SystemVerilog, timing analysis, and advanced design methods while contributing to state-of-the-art automotive

Qualifications

• BS and/or MS in Electrical Engineering, Computer Science, or related field.
• Minimum 10+ years of ASIC RTL design and/or architecture experience.
• Proven track record with the development of complex SoCs.
• Strong understanding of digital design fundamentals and methodologies.
• In-depth knowledge of Verilog/System Verilog and simulation tools.
• Self-motivated and able to work effectively both independently and in a team.

Responsibilities

• Own RTL design, verification, and timing for automotive SoCs.
• Collaborate with system architects, software, hardware, and verification teams.
• Define ASIC internal/external interfaces and data flows.
• Work with minimal supervision as a self-starter.
• Hybrid work location in San Jose, CA.

Skills

ASIC RTL design

Digital design

Verilog/SystemVerilog

Leadership

Education

BS/MS in Electrical Engineering/CS

Tools

Simulation tools

Verilog

Job description

Ethernovia, Inc. is seeking a Senior ASIC Front-End Design Engineer in San Jose, CA on a hybrid schedule. You will own RTL design, verification, and timing for automotive SoCs, collaborating with system architects and cross-functional teams to deliver high-performance, power-efficient ASICs.

A self-driven leader with 10+ years in ASIC RTL is ideal for this role. You’ll work with Verilog/SystemVerilog, timing analysis, and advanced design methods while contributing to state-of-the-art automotive