Senior ASIC Verification Engineer - Pre-IPO Stock Options

Ethernovia; San Jose (CA); On-site; USD 200,000 - 300,000; Full time

Benefits offered by this job

Pre IPO stock options

Flexible hours

Medical, dental and vision insurance

Job summary

Ethernovia, Inc. is seeking a Senior ASIC Verification Engineer in San Jose, CA to lead all aspects of digital SoC verification. You will work with architects, designers, and SW engineers to plan and execute verification for automotive communication semiconductors and systems.

The role requires 10+ years in ASIC verification, strong SystemVerilog/UVM experience, and collaboration across multidisciplinary teams. Competitive salary and benefits accompany the position.

Qualifications

• BS or MS in Electrical Engineering, Computer Science, or related field.
• Minimum 10+ years of ASIC verification experience.
• Strong understanding of ASIC verification fundamentals and industry standard methodologies.
• Experience with Verilog/SystemVerilog, UVM, Python, TCL, C/C++.
• Experience with full verification flow from spec to coverage analysis to gate level sim.
• Debugging failures in simulation to root cause problems.
• Self-motivated and able to work effectively independently and in a team.

Responsibilities

• Plan and execute verification and validation of advanced automotive communication semiconductors and systems.
• Collaborate with architects, designers, and SW engineers to ensure verification coverage.
• Contribute to a positive, cohesive working environment based on integrity and strong work ethics.

Skills

ASIC verification

SystemVerilog

Python

C/C++

Debugging

Education

BS/MS in Electrical Engineering, Computer Science, or related field

Tools

Verilog

UVM

TCL

SystemC

DPI

Job description

Ethernovia, Inc. is seeking a Senior ASIC Verification Engineer in San Jose, CA to lead all aspects of digital SoC verification. You will work with architects, designers, and SW engineers to plan and execute verification for automotive communication semiconductors and systems.

The role requires 10+ years in ASIC verification, strong SystemVerilog/UVM experience, and collaboration across multidisciplinary teams. Competitive salary and benefits accompany the position.