Senior ASIC Engineer - Onsite in San Jose, AI Hardware

Cisco Systems; San Jose (CA); On-site; USD 180,000 - 260,000; Full time

Job summary

Cisco Systems seeks an experienced ASIC Design Engineer in San Jose to drive the architecture, design and verification of high-performance ASICs. You will own multiple functional areas, develop reusable code, and debug across ASIC, software and hardware layers.

Preferred candidates have UVM verification leadership, Linux/C++/Python proficiency, and emulation experience (Veloce/Palladium/Zebu/HAPS). The role is onsite four days a week in San Jose, CA, with extensive lab bring-up and power

Qualifications

• Minimum: Bachelor’s degree in EE/CS or related field with 7+ years of ASIC design/verification experience.
• Strong SystemVerilog-based design/verification experience and debugging skills.
• Experience leading verification methodology in UVM for clusters or full chip.
• Experience with emulation platforms (Veloce, Palladium, Zebu, HAPS).
• Proficient in Linux, C/C++, and Python/Perl.
• Networking experience is a plus.

Responsibilities

• Drive definition, architecture and verification of high performance ASICs.
• Own complex or multiple functional areas.
• Develop reusable code for future projects.
• Debug at ASIC, SW, HW level.
• Lead code reviews at platform level.
• Define new verification methodologies.
• Assist in lab bring up.
• Identify power saving solutions.

Skills

ASIC design

SystemVerilog

Debugging

UVM verification

C/C++

Python/Perl

Networking

Education

Bachelor's degree in Electrical Engineering or related field

Tools

Veloce

Palladium

Zebu

HAPS

Job description

Cisco Systems seeks an experienced ASIC Design Engineer in San Jose to drive the architecture, design and verification of high-performance ASICs. You will own multiple functional areas, develop reusable code, and debug across ASIC, software and hardware layers.

Preferred candidates have UVM verification leadership, Linux/C++/Python proficiency, and emulation experience (Veloce/Palladium/Zebu/HAPS). The role is onsite four days a week in San Jose, CA, with extensive lab bring-up and power