Senior ASIC Engineer - Hybrid, High-Performance Design

Cisco Systems; San Jose (CA); Hybrid; USD 138,000 - 197,000; Full time

Job summary

Cisco is seeking an ASIC Engineer (hybrid) in San Jose to define, design and verify ASICs and subsystems for Cisco platforms. You will collaborate within a multi-disciplinary team to meet power, performance, and area goals and help define processes and tools for complex design and tapeout.

The role emphasizes ownership of high-complexity code, design verification leadership, and milestone-driven development, with a strong focus on analog/mixed-signal considerations and physical design.

Qualifications

• Minimum Qualifications: Typically: Bachelor’s + 5 years of related experience, or Master’s + 3 years of related experience, or PhD + 0 years of related experience
• Preferred Qualifications Varies based on the team and business needs | Preferred Qualifications are desired education, experience, and skills that are in addition to Minimum Qualifications

Responsibilities

• Collaborates on the definition and design of high performance ASICs
• Oversees project code
• Owns complex code, and debugs within and outside of owned code
• Documents functional and user specs for code
• Builds out design by completing block level flow, from block spec to tapeout
• Contributes to resolution of block level issues
• Writes and executes test plans and test benches
• Leads design verification activities
• Leads reviews for owned code
• Writes and executes test plans and test benches concerning analog/mixed signal products
• Owns physical design of multiple blocks or one high complexity block
• Guides RDL block owners on RTL changes
• Drives Signal and Power integrity for the ASIC integration
• Understands and drives development milestones to success
• Analyzes and validates subsystems

Education

Bachelor's degree

Master's degree

PhD

Job description

Cisco is seeking an ASIC Engineer (hybrid) in San Jose to define, design and verify ASICs and subsystems for Cisco platforms. You will collaborate within a multi-disciplinary team to meet power, performance, and area goals and help define processes and tools for complex design and tapeout.

The role emphasizes ownership of high-complexity code, design verification leadership, and milestone-driven development, with a strong focus on analog/mixed-signal considerations and physical design.