Senior ASIC Design Engineer for AI/HPC Networking (Remote)

Cornelis Networks, Inc.; United States; Remote; USD 140,000 - 230,000; Full time

Benefits offered by this job

Equity

Cash incentives

Health benefits

401(k) with company match

Open Time Off

Job summary

Cornelis Networks, Inc. is seeking Senior ASIC Design Engineers with deep expertise in RTL, Verilog/SystemVerilog, high‑speed data paths, and Ethernet host adapters to help build world‑class SoCs for AI and HPC applications.

You will collaborate with hardware, firmware, and software teams across multiple states and support post‑silicon validation, timing closure, and performance/power optimizations. We offer equity, competitive incentives, comprehensive health and retirement benefits, and

Qualifications

• 8+ years of post‑college experience in digital design with Verilog and SystemVerilog.
• Experience in RTL design for high‑speed data paths or packet processing in ASICs.
• Deep understanding of Host Ethernet adaptor architectures.
• Familiarity with timing closure and modern physical design methodologies.
• Proven ability in system-level debug and root cause analysis of technical issues.
• Strong verbal and written communication skills.

Responsibilities

• Implement RTL designs using Verilog/SystemVerilog for high‑speed data paths and packet processing logic.
• Collaborate with verification engineers to create block- and system‑level test plans to ensure comprehensive design coverage.
• Define timing constraints for RTL blocks and work with Physical Design engineers to optimize timing closure.
• Support post-silicon validation, collaborating with hardware, firmware, and software teams to debug and resolve ASIC issues.
• Contribute to performance optimization and power‑aware design strategies for Host Fabric Interface subsystems.

Skills

Verilog

SystemVerilog

RTL design

High-speed data paths

Networking protocols

Debugging

Communication

Education

B.S. or M.S. in Computer/ Electrical Engineering

Tools

Design Compiler

PrimeTime

Python

TCL

Job description

Cornelis Networks, Inc. is seeking Senior ASIC Design Engineers with deep expertise in RTL, Verilog/SystemVerilog, high‑speed data paths, and Ethernet host adapters to help build world‑class SoCs for AI and HPC applications.

You will collaborate with hardware, firmware, and software teams across multiple states and support post‑silicon validation, timing closure, and performance/power optimizations. We offer equity, competitive incentives, comprehensive health and retirement benefits, and