Senior ASIC Design Engineer

Cisco; San Jose (CA); Hybrid; USD 149,000 - 215,000; Full time

Job summary

An innovative company is seeking a Senior ASIC Design Engineer to join their Silicon One team. This role involves developing cutting-edge silicon architecture for web-scale networks, where you'll write specifications, implement Verilog RTL, and collaborate with cross-functional teams to ensure design integrity. With a focus on fostering inclusion and community involvement, this firm promotes a hybrid work culture that encourages learning and development. If you're passionate about technology and eager to make an impact, this position offers a unique opportunity to contribute to a leading organization in the tech industry.

Benefits

Hybrid work culture

Employee resource groups

Paid volunteer time

Qualifications

• 7+ years of ASIC design experience or 4+ years with a Master's degree.
• Experience with Verilog/SystemVerilog and debugging methodologies.

Responsibilities

• Write micro-architecture specifications and implement Verilog RTL.
• Collaborate with teams to address bugs and perform validation tests.

Skills

Verilog

SystemVerilog

ASIC design

Debugging methodologies

Scripting (Python, Perl, TCL, shell)

Education

Bachelor's Degree in Electrical or Computer Engineering

Master's Degree in Electrical or Computer Engineering

Tools

VCS

DC

PrimeTime

Job description

Join to apply for the Senior ASIC Design Engineer role at Cisco.

3 days ago Be among the first 25 applicants.

This range is provided by Cisco. Your actual pay will be based on your skills and experience — talk with your recruiter to learn more.

Base pay range

$149,600.00/yr - $214,100.00/yr

The application window is expected to close on: for U.S. May 9th, 2025.
Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received.

Meet the Team

Join the Cisco Silicon One team in developing a unified silicon architecture for web-scale and service provider networks. Cisco's silicon team offers a unique experience by combining resources from a large, multi-geography organization and a startup culture with growth opportunities.

Your Impact

• Write micro-architecture specifications and participate in reviews.
• Implement Verilog RTL to meet timing, performance, and power requirements.
• Contribute to full chip integration and timing methodology/analysis.
• Develop and analyze functional coverage.
• Help define, evolve, and support our design methodology.
• Collaborate with verification and physical design teams to address bugs, timing, and routing issues.
• Triage, debug, and root cause simulation, software bring-up, and customer failures.
• Perform diagnostic and post-silicon validation tests in the lab.

Minimum Qualifications

• Bachelor's Degree in Electrical or Computer Engineering with 7+ years of ASIC design experience or Master's Degree with 4+ years.
• Experience with Verilog or SystemVerilog programming.
• Experience with simulators, synthesis, static timing constraints, and tools like VCS, DC, PrimeTime.
• Experience with debugging and verification methodologies.

Preferred Qualifications

• Understanding of Networking technologies.
• Scripting experience (Python, Perl, TCL, shell).
• Experience with formal verification tools and emulation.

Additional Information

#WeAreCisco — celebrating diversity, fostering inclusion, and supporting community involvement.

Our culture promotes hybrid work, learning, and development, with initiatives like employee resource groups and paid volunteer time.

Join us to be part of a company that powers the internet and drives an inclusive future for all.