Senior ASIC Design Engineer

Stier Solutions Inc; San Jose (CA); On-site; USD 120,000 - 160,000; Full time

Job summary

Join a forward-thinking company as a Mid-Senior Level Engineer, where your expertise in FPGA design and ASIC development will be invaluable. You'll engage in mapping multi-million gate SoC designs onto advanced prototyping platforms while collaborating with cross-functional teams to validate performance objectives. With a focus on innovation, you'll have the opportunity to contribute to the evolution of prototyping methodologies and tackle complex design challenges. If you're passionate about cutting-edge technology and ready to make a significant impact in the engineering field, this role offers an exciting path forward.

Qualifications

• 10+ years of experience in ASIC design or 8+ years with a Master's degree.
• Expertise in FPGA design and multi-million gate designs.

Responsibilities

• Map multi-million gate SoC designs onto prototyping platforms.
• Collaborate with teams to validate SoC functional and performance objectives.

Skills

FPGA design

RTL coding using Verilog/System Verilog

Synthesis, place, and route flows for FPGAs

Digital design concepts

Scripting languages (TCL, Python, Perl)

Education

Bachelor's Degree in Electrical or Computer Engineering

Master's Degree in Electrical or Computer Engineering

Tools

HAPS

Cadence Z2

Zebu

Job description

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• Map multi-million gate SoC designs onto prototyping platforms, creating design partitions, FPGA builds, and testbenches to simulate FPGA components.

• Establish prototyping systems in the lab and contribute to defining, evolving, and supporting our prototyping methodology.

• Option to engage in block-level RTL design or block or top-level IP integration.

• Collaborate with Software, Design, and Verification teams to validate the functional and performance objectives of the SoC.

What we are looking for:

• A bachelor’s degree in electrical or computer engineering, with a minimum of 10 years of experience in ASIC or a related field, or a Master's Degree in Electrical or Computer Engineering with at least 8 years of experience in ASIC or a related discipline.

• A comprehensive understanding of FPGA design, with proven expertise in partitioning multi-million gate designs across multiple FPGAs.

• Proficiency in synthesis, place, and route flows for FPGAs.

• An in-depth knowledge of digital design concepts, including Clock Domain Crossing (CDC) and Reset Domain Crossing (RDC).

• Demonstrated experience in RTL coding using Verilog/System Verilog and integration of third-party IPs.

• A meticulous and methodical approach to triaging, debugging, and identifying root causes of issues throughout various phases of FPGA development.

Preferred Qualifications

• Experience in prototyping Networking System-on-Chips (SoCs) on HAPS or Cadence Z2 or Zebu equivalent prototyping platforms.

• A strong understanding of PCIE, DDR, Ethernet, and Networking Protocols.

• Proficiency in prototyping ARM or RISCV CPUs.

• Exceptional scripting skills using languages such as TCL, Python, or Perl.

Seniority level

• Mid-Senior level

Employment type

• Full-time

Job function

• Engineering and Information Technology