Senior ASIC Design Engineer

Cisco; San Jose (CA); On-site; USD 149,000 - 215,000; Full time

Job summary

A leading company is seeking a Senior ASIC Design Engineer to join their Silicon One team in San Jose, CA. This role involves developing a unified silicon architecture and collaborating with various teams to ensure design integrity. Ideal candidates will have extensive ASIC design experience and proficiency in Verilog. The position offers a competitive salary and a commitment to diversity and inclusion.

Benefits

Paid volunteer time

Employee resource organizations

Culture of learning and development

Qualifications

• 7+ years of ASIC design experience or 4+ years with a Master's.
• Experience with debugging and verification methodologies.

Responsibilities

• Write micro-architecture specifications and participate in reviews.
• Implement Verilog RTL to meet timing, performance, and power requirements.
• Collaborate with verification and physical design teams.

Skills

Verilog

System Verilog

Debugging

Scripting

Education

Bachelor's Degree in Electrical or Computer Engineering

Master's Degree

Tools

VCS

DC

PrimeTime

Job description

Join to apply for the Senior ASIC Design Engineer role at Cisco

Base pay range

$149,600.00/yr - $214,100.00/yr

Application deadline and location

The application window is expected to close on 4/30/2025. This is an onsite position located in San Jose, CA.

Meet the Team

Join the Cisco Silicon One team in developing a unified silicon architecture for web-scale and service provider networks. Cisco's silicon team offers a unique experience by combining extensive resources with a startup culture and growth opportunities.

Your Impact

• Write micro-architecture specifications and participate in reviews.
• Implement Verilog RTL to meet timing, performance, and power requirements.
• Contribute to full chip integration and timing methodology/analysis.
• Develop and analyze functional coverage.
• Help define, evolve, and support our design methodology.
• Collaborate with verification and physical design teams to address design bugs, timing, and routing issues.
• Triaging, debugging, and root cause analysis of simulation, software, and customer failures.
• Perform diagnostic and post-silicon validation tests in the lab.

Minimum Qualifications

• Bachelor's Degree in Electrical or Computer Engineering with 7+ years of ASIC design experience or Master's Degree with 4+ years.
• Experience with Verilog or System Verilog programming.
• Familiarity with simulators, synthesis, static timing constraints, and related tools (e.g., VCS, DC, PrimeTime).
• Experience with debugging and verification methodologies.

Preferred Qualifications

• Understanding of networking technologies and concepts.
• Scripting experience (Python, Perl, TCL, shell).
• Experience with formal verification tools and emulation.

Additional Information

We celebrate diversity and inclusion, offering resources like employee resource organizations, paid volunteer time, and a culture of learning and development. Join us to help power an inclusive future for all.