Job opportunity for Senior ASIC Design Engineer - San Jose, CA (onsite)

Cybotic Systems; California; On-site; USD 120,000 - 160,000; Full time

Job summary

A leading company in the tech industry is seeking an experienced engineer to work on multi-million gate SoC designs. The ideal candidate will have extensive experience in FPGA design and ASIC development, contributing to the prototyping methodology and collaborating with various teams to ensure performance objectives are met.

Qualifications

• Minimum 10 years experience in ASIC or 8 years with a Master's degree.
• Proficient with the entire HAPS flow and experience in triaging HAPS systems.

Responsibilities

• Map multi-million gate SoC designs onto prototyping platforms.
• Collaborate with teams to validate functional and performance objectives.

Skills

FPGA design

RTL coding

Debugging

Scripting

Education

Bachelor's degree in Electrical Engineering

Master's degree in Electrical Engineering

Tools

HAPS

Cadence Z2

Zebu

Job description

Location : San Jose, CA (Complete onsite)

Experience : 8+ years (Relevant)

What candidate will Be Doing :

• Map multi-million gate SoC designs onto prototyping platforms, creating design partitions, FPGA builds, and testbenches to simulate FPGA components.
• Establish prototyping systems in the lab and contribute to defining, evolving, and supporting our prototyping methodology.
• Option to engage in block-level RTL design or block or top-level IP integration.
• Collaborate with Software, Design, and Verification teams to validate the functional and performance objectives of the SoC.

What we are looking for :

• A bachelor's degree in electrical or computer engineering, accompanied by a minimum of 10 years of experience in ASIC or a related field, or a master's degree in electrical or computer engineering with at least 8 years of experience in ASIC or a related discipline.
• A comprehensive understanding of FPGA design, with proven expertise in partitioning multi-million gate designs across multiple FPGAs.
• Proficiency in synthesis, place, and route flows for FPGAs.
• An in-depth knowledge of digital design concepts, including Clock Domain Crossing (CDC), Reset Domain Crossing (RDC).
• Demonstrated experience in RTL coding using Verilog / System Verilog and integration of third-party IPs.
• A meticulous and methodical approach to triaging, debugging, and identifying root causes of issues throughout various phases of FPGA development.
• Our expectation is that candidate is proficient with the entire HAPS flow not just limited to building images
• Having the experience to setup HAPS systems and triage issues around HAPS bringup is must for this position

Preferred Qualifications

• Experience in prototyping Networking System-on-Chips (SoCs) on HAPS or Cadence Z2 or Zebu equivalent prototyping platforms.
• A strong understanding of PCIE, DDR, Ethernet, and Networking Protocols.
• Proficiency in prototyping ARM or RISCV CPUs.
• Exceptional scripting skills using languages such as TCL, Python, or Perl.

Must Have Skills :

• Our expectation is that candidate is proficient with the entire HAPS flow not just limited to building images
• Having the experience to setup HAPS systems and triage issues around HAPS bringup is must for this position

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