Senior ASIC CPU/SoC Architect - High-Performance Networking

Cisco Systems, Inc.; San Jose (CA); On-site; USD 187,000 - 268,000; Full time

Benefits offered by this job

Medical Insurance

401(k) Matching

Paid Parental Leave

Stock-based compensation

Job summary

Cisco Systems, Inc. in San Jose is seeking a senior designer to lead architecture and design of complex CPU subsystems for next‑gen high‑performance networking switch ASICs.

You will guide RTL development, pre/post-silicon work, and collaborate with SDK, BSP, and Network OS teams. You will work across silicon and software teams to define interfaces, ensure memory consistency, and support early emulation and FPGA validation, enabling scalable, secure networking hardware for enterprise and cloud

Qualifications

• Experience with microarchitectural CPU ecosystems (RISC-V, ARM, or ARC).
• Experience with on-chip interconnect fabrics (AXI/CHI/NoC).
• Experience with PCIe subsystems and ASIC/SoC design flow (RTL, pre-silicon verification, timing, post-silicon bring-up).
• Proficiency in SystemVerilog RTL development and related flows.

Responsibilities

• Lead architecture and design of complex CPU subsystems for next‑gen high‑performance networking switch ASICs.
• Define driver interfaces, register maps, and memory consistency models with software teams.
• Collaborate with SDK, BSP, NOS teams and support early emulation and FPGA platforms.

Skills

Microarchitectural CPU ecosystems (RIS

On-chip interconnect fabrics (AXI/CHI/

PCIe subsystems

SystemVerilog RTL design

Education

Bachelor's + 8 years experience

Master's + 6 years experience

PhD + 3 years experience

Job description

Cisco Systems, Inc. in San Jose is seeking a senior designer to lead architecture and design of complex CPU subsystems for next‑gen high‑performance networking switch ASICs.

You will guide RTL development, pre/post-silicon work, and collaborate with SDK, BSP, and Network OS teams. You will work across silicon and software teams to define interfaces, ensure memory consistency, and support early emulation and FPGA validation, enabling scalable, secure networking hardware for enterprise and cloud