Senior ASIC Architect for AI Accelerators | SoC Design

Delos Data; Palo Alto (CA); Hybrid; USD 160,000 - 280,000; Full time

Benefits offered by this job

Equity

401k

Benefits

Job summary

Delos Data is seeking a visionary ASIC Architect to define and guide the development of next-generation, high-performance ASICs for AI accelerators and datacenter workloads.

You will translate system requirements into architectural specifications, balancing power, performance, and area while collaborating across RTL, verification, physical design, firmware, and software teams. The role emphasizes leadership, PPA optimization, and pre-silicon modeling to ensure robust, scalable silicon solutions.

Qualifications

• Bachelor’s degree in Electrical Engineering, Computer Engineering, or Computer Science
• 7+ years of experience in ASIC architecture, micro-architecture, or high-level design
• Strong proficiency in SystemVerilog/Verilog and C/C++ or SystemC for modeling
• Deep knowledge of computer architecture, including CPU/GPU cores, caches, fabric, and memory hierarchies
• Experience with Ethernet, PCIe, or UCIe protocols
• Familiarity with EDA tools such as Synopsys Design Compiler, Cadence Genus, or similar
• Experience with performance modeling and analysis tools

Responsibilities

• Lead the creation of Architectural Design Specifications (ADS) and Micro-architecture Specifications (MAS) for complex ASICs
• Develop high-level performance models to analyze workload behaviors and validate architectural assumptions
• Optimize chip-level and block-level architecture to meet power, performance, and area goals
• Partner with RTL design, verification, physical design, firmware, and software teams for implementation and validation
• Drive architectural trade-off studies and lead design reviews
• Define advanced power management strategies including DVFS, power domains, and clock gating
• Mentor junior engineers and contribute to technical leadership

Skills

SystemVerilog/Verilog

C/C++

SystemC

Computer architecture

Performance modeling

Education

Bachelor’s degree in Electrical Engineering or Computer Engineering or Computer Science

Master’s degree

PhD

Tools

Synopsys Design Compiler

Cadence Genus

Job description

Delos Data is seeking a visionary ASIC Architect to define and guide the development of next-generation, high-performance ASICs for AI accelerators and datacenter workloads.

You will translate system requirements into architectural specifications, balancing power, performance, and area while collaborating across RTL, verification, physical design, firmware, and software teams. The role emphasizes leadership, PPA optimization, and pre-silicon modeling to ensure robust, scalable silicon solutions.