Senior ASIC Architect for AI Accelerators & SoCs

Delos Data Inc

Iowa

Hybride

USD 160 000 - 280 000

Plein temps

Il y a 4 jours
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Avantages offerts par ce poste

Equity
Benefits
401k

Résumé du poste

Delos Data Inc. is seeking an experienced ASIC Architect to define and guide the development of next‑generation, high‑performance ASICs for AI accelerators and datacenter workloads.

You will translate system requirements into architectural specifications, balancing power, performance, and area, and collaborate across RTL, verification, physical design, firmware, and software teams. You will lead architectural design specifications, model workloads, and drive design reviews while mentoring

Qualifications

  • Bachelor's degree in Electrical Engineering or Computer Science; relevant experience mandatory.
  • Master's or PhD preferred with strong research background.

Responsabilités

  • Lead the creation of Architectural Design Specifications (ADS) and Micro-architecture Specifications (MAS) for complex ASICs including high-speed interconnect fabric and IO protocols (Ethernet, PCIe, UCIe).
  • Develop high-level performance models (SystemC/TLM, C++, or Python) to analyze workload behaviors and validate architectural assumptions.
  • Optimize chip-level and block-level architecture to meet stringent power, performance, and area goals.
  • Partner with RTL design, verification, physical design, firmware, and software teams to ensure seamless implementation and validation.
  • Drive architectural trade-off studies and lead design reviews.
  • Define advanced power management strategies including DVFS, power domains, and clock gating.
  • Mentor junior engineers and contribute to technical leadership across the organization.

Connaissances

ASIC architecture
SystemVerilog/Verilog
C/C++/SystemC modeling
Block/SoC integration
PPA optimization
Cross-team collaboration
Performance modeling
Python scripting

Formation

Bachelor's degree in Electrical Engineering
Master's or PhD preferred

Outils

Synopsys Design Compiler
Cadence Genus

Description du poste

Delos Data Inc. is seeking an experienced ASIC Architect to define and guide the development of next‑generation, high‑performance ASICs for AI accelerators and datacenter workloads.

You will translate system requirements into architectural specifications, balancing power, performance, and area, and collaborate across RTL, verification, physical design, firmware, and software teams. You will lead architectural design specifications, model workloads, and drive design reviews while mentoring

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