Senior Analog/Mixed-Signal IC Designer — LNA & ADC, Equity

Triveni IT; Santa Clara (CA); Sur place; USD 180 000 - 280 000; Plein temps

Avantages offerts par ce poste

Equity opportunities

Résumé du poste

Triveni IT is seeking a Senior Analog / Mixed-Signal IC Design Engineer to join its semiconductor design team in Santa Clara. You will lead architecture, design, and silicon validation for high-performance analog and mixed-signal blocks, focusing on LNA, ADC architectures, and sensor readout circuits.

The ideal candidate has 12–15+ years of experience in analog/mixed-signal IC design, proficiency with Cadence Virtuoso/Spectre and Calibre, and hands-on experience with deep-submicron CMOS

Qualifications

• 13–15+ years of analog/mixed-signal IC design experience.
• Bachelor's, Master's, or Ph.D. in Electrical Engineering, Microelectronics, VLSI Design, or related field.

Responsabilités

• Lead architecture, design, simulation, and silicon validation of analog and mixed-signal IC blocks.
• Design Low-Noise Amplifiers (LNA) with noise optimization.
• Develop ADC architectures (column-parallel ADCs for imaging/sensing).
• Design ultra-low-power analog circuits in deep-submicron CMOS technologies.
• Work on high-density data conversion and sensor readout circuits.
• Perform circuit simulations, PVT analysis, Monte Carlo analysis, and design verification.
• Collaborate with layout, verification, process, and system teams through tape-out and silicon bring-up.
• Support laboratory characterization and debug of fabricated silicon.

Connaissances

Analog IC design

Mixed-signal design

LNA design

ADC design

Sensor readout circuits

Circuit simulations

PVT analysis

Monte Carlo analysis

Tape-out

Silicon bring-up

CMOS process technology

Team collaboration

Formation

Electrical Engineering / Microelectronics / VLSI Design

Outils

Cadence Virtuoso

Cadence Spectre

Calibre

Description du poste

Triveni IT is seeking a Senior Analog / Mixed-Signal IC Design Engineer to join its semiconductor design team in Santa Clara. You will lead architecture, design, and silicon validation for high-performance analog and mixed-signal blocks, focusing on LNA, ADC architectures, and sensor readout circuits.

The ideal candidate has 12–15+ years of experience in analog/mixed-signal IC design, proficiency with Cadence Virtuoso/Spectre and Calibre, and hands-on experience with deep-submicron CMOS