Analog IC Design Engineer

Anysilicon; Tempe, Northern (AZ, KY); Hybrid; USD 140,000 - 170,000; Full time

Job summary

Anysilicon in Tempe, AZ seeks an Analog/Mixed-Signal IC Design Engineer to develop high-performance ADCs, DACs, RF front ends and other signal-chain blocks for advanced communication and sensing systems. You will use Cadence Virtuoso/Spectre, MATLAB, Verilog-A and Verilog/SystemVerilog to design, simulate and verify silicon blocks, and collaborate with layout for tapeout readiness.

Ph.D. preferred; strong lab testing and tapeout experience in advanced CMOS technologies, plus hands-on debugging,

Qualifications

• Ph.D. in Electrical Engineering or related field preferred.
• Proven tapeout experience in advanced CMOS technologies.
• Experience designing high-speed ADCs; DACs and RF circuits preferred.

Responsibilities

• Design and optimize high-performance analog/mixed-signal blocks (ADC/DAC, RF front ends).
• Develop transistor-level schematics and run Cadence simulations.
• Build system models using MATLAB, Verilog-A, and Verilog/SystemVerilog.
• Collaborate with layout for floorplanning, device matching, shielding, and layout optimization.
• Perform post-layout verification and extraction and support tapeout signoff.
• Develop silicon validation plans and guide lab testing for performance characterization.

Skills

High-speed design

Lab testing

Independent work

Communication

Education

Ph.D. in Electrical Engineering

Tools

Cadence Virtuoso/Spectre

MATLAB

Verilog-A

Verilog/SystemVerilog

Cadence Pegasus

Siemens Calibre

Job description

Join our innovative team as an Analog/Mixed-Signal IC Design Engineer, focusing on developing high-performance ADC/DAC, RF transmitter/receiver, and mixed-signal signal-chain building blocks for advanced communication and sensing systems. This role involves working with deep submicron CMOS technologies (22 nm, 12 nm, 7 nm) and encompasses architecture definition, circuit design, modeling, layout support, verification, tapeout, and silicon validation. Ideal for experienced engineers with a strong background in high-speed ADC/DAC design and hands-on lab testing capabilities.

Responsibilities:

• Design, analyze, and optimize high-performance analog and mixed-signal IC blocks, including high-speed ADCs, DACs, RF transmitter/receiver front ends, and other signal-chain building blocks.
• Develop transistor-level schematics and perform circuit simulations using Cadence Virtuoso/Spectre, including various analyses.
• Build and maintain system-level and behavioral models using MATLAB, Verilog-A, and Verilog/SystemVerilog.
• Collaborate with layout engineers for floorplanning, device matching, shielding, and layout optimization.
• Perform post-layout verification and extraction using Cadence Pegasus, Calibre, and related flows.
• Support full-chip integration, including interface definition and top-level verification.
• Lead or support tapeout activities, including schematic/layout reviews and documentation preparation.
• Develop silicon validation plans and guide lab testing for performance characterization.
• Analyze silicon measurement data, debug performance issues, and provide design improvement recommendations.
• Prepare technical documentation, datasheets, and customer-facing materials.

Qualifications:

• Ph.D. in Electrical Engineering, Microelectronics, or a related field preferred.
• Strong experience in analog/mixed-signal IC design with proven tapeout experience in advanced CMOS technologies.
• Demonstrated experience designing high-speed ADCs is required; experience with DACs and RF circuits is preferred.
• Strong understanding of ADC/DAC architectures and high-speed data-converter performance tradeoffs.
• Experience with MATLAB-based system modeling and calibration modeling.
• Experience developing and using Verilog-A and Verilog/SystemVerilog models for mixed-signal design.
• Proficiency with Cadence design tools, including Virtuoso and Spectre.
• Hands-on experience with physical verification and extraction tools like Cadence Pegasus and Siemens Calibre.
• Experience with post-layout simulation and tapeout signoff flows.
• Hands-on lab testing experience with high-speed ADC/DAC or RF ICs.

Skills:

• Strong communication skills to work across teams.
• Ability to work independently in a fast-paced environment.
• Expertise in high-speed ADC/DAC design and lab testing.
• Proficiency in Cadence design tools and MATLAB.
• Experience with silicon validation and debugging.