Senior Analog/Mixed-Signal IC Designer

Blue Origin; San Diego (CA); Sur place; USD 230 000 - 323 000; Plein temps

Avantages offerts par ce poste

Medical insurance

Dental insurance

Vision insurance

401(k) with company match

Paid parental leave

Stock options

Résumé du poste

Blue Origin in San Diego/Cupertino seeks a Senior-level Mixed-Signal / Custom Digital IC Designer to develop, simulate, and deliver Liberty timing models for custom analog-digital interfaces in complex ICs.

You will work with analog, digital, STA, verification, and physical design teams to ensure accurate timing models, SPICE-level validation, and library characterization across PVT corners. On-site in CA with remote exception during site development.

Qualifications

• BS or MS in Electrical Engineering or related field.
• 7+ years of relevant experience in custom IC design or digital timing methodology.
• Experience with transistor-level SPICE simulations.
• Strong understanding of CMOS digital design and timing concepts.

Responsabilités

• Generate and maintain Liberty .lib models for custom digital and analog-digital interface circuits.
• Characterize timing across PVT corners, input slew, output load, and parasitics.
• Validate .lib files against transistor-level simulations and STA results.
• Develop and automate characterization flows using Python, Tcl, or SKILL.
• Collaborate with digital design, STA, verification, and physical design teams.

Connaissances

Transistor-level design

Digital timing concepts

Liberty timing models

Scripting (Python, Tcl, Perl, shell)

Cross-functional collaboration

Formation

BS or MS in Electrical Engineering

Outils

Cadence Virtuoso

Spectre/HSPICE

PrimeTime/Tempus

Liberty characterization tools

Synthesis/Place‑&‑Route flows

Description du poste

Blue Origin in San Diego/Cupertino seeks a Senior-level Mixed-Signal / Custom Digital IC Designer to develop, simulate, and deliver Liberty timing models for custom analog-digital interfaces in complex ICs.

You will work with analog, digital, STA, verification, and physical design teams to ensure accurate timing models, SPICE-level validation, and library characterization across PVT corners. On-site in CA with remote exception during site development.