Senior Analog IC Design & Verification Engineer (SoC)

Roboticsconnected

Austin (TX)

In loco

USD 125.000 - 291.000

Tempo pieno

14 giorni+

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Il tuo curriculum e una lettera di presentazione personalizzati, che corrispondono esattamente a ciò che sta cercando.

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Vantaggi offerti da questo lavoro

Medical, dental, vision insurance (PPO
Equity (RSUs)
401(k) plan
Paid holidays
Commuter benefits
Meals provided
Parental leave
Flexible time off

Descrizione del lavoro

Neuralink seeks an engineer to lead analog and mixed-signal chip design, from circuit concepts to layout and verification. You will simulate, validate, and optimize blocks such as DACs/ADCs, PLLs, and high-speed PHYs while mentoring junior engineers and coordinating with layout teams.

The role emphasizes tight collaboration with internal users and vendors to meet strict performance and cost targets, with base salary plus RSUs and full-time benefits.

Competenze

  • BS in electrical engineering or related field with 5+ years of experience after degree.
  • 5+ years analog/mixed-signal CMOS design with silicon validation.
  • Strong analytical and problem-solving abilities.

Mansioni

  • Design analog circuit blocks and subsystems at transistor level to meet noise, mismatch, distortion, and power constraints.
  • Oversee block-level layout with layout teams.
  • Plan and execute analog verification and run complex simulations (power, performance, yield).
  • Mentor and review tests; identify and analyze bugs and issues.
  • Collaborate with internal/external users and vendors to align implementations with needs.

Conoscenze

Analog/mixed-signal design
Circuit design
Analytical mindset
Mentoring junior engineers

Formazione

Bachelor of Science in Electrical Engineering or related field
Masters or PhD in EE/Physics (preferred)

Strumenti

Verilog AMS
SystemVerilog
SPICE/simulation tools

Descrizione del lavoro

Neuralink seeks an engineer to lead analog and mixed-signal chip design, from circuit concepts to layout and verification. You will simulate, validate, and optimize blocks such as DACs/ADCs, PLLs, and high-speed PHYs while mentoring junior engineers and coordinating with layout teams.

The role emphasizes tight collaboration with internal users and vendors to meet strict performance and cost targets, with base salary plus RSUs and full-time benefits.

Ottieni la revisione del curriculum gratis e riservata.

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