Senior Analog IC Design & Verification Engineer

Neuralink; South San Francisco (CA); On-site; USD 125,000 - 291,000; Full time

Benefits offered by this job

Equity (RSUs)

Medical, dental, vision insurance

401(k) plan

Job summary

Neuralink seeks an experienced analog/mixed-signal IC engineer to design and verify CMOS circuits for high-speed brain-machine interface SoCs. Responsibilities include circuit design, layout oversight, and analog verification with a focus on noise, distortion, and power trade-offs.

The role requires a BS with 5+ years in related fields; MS/PhD is a plus. Employment offers equity (RSUs) and full-time compensation in a cutting-edge team.

Qualifications

• Bachelor of Science degree with 5+ years in related field.
• Experience in analog/mixed-signal CMOS design with silicon validation.
• Interest in building and solving problems across analog turbo areas.

Responsibilities

• Design analog circuit building blocks and subsystems at transistor level.
• Oversee block-level layout with layout teams.
• Plan and execute analog verification and run complex simulations.
• Mentor junior teammates and review tests.
• Collaborate with internal/external users to align with needs.

Skills

Analog/mixed-signal design

CMOS design

Verilog AMS

SystemVerilog

Education

BS in Electrical Engineering + 5 years

MS or PhD in EE

Tools

Verilog AMS

SystemVerilog

Job description

Neuralink seeks an experienced analog/mixed-signal IC engineer to design and verify CMOS circuits for high-speed brain-machine interface SoCs. Responsibilities include circuit design, layout oversight, and analog verification with a focus on noise, distortion, and power trade-offs.

The role requires a BS with 5+ years in related fields; MS/PhD is a plus. Employment offers equity (RSUs) and full-time compensation in a cutting-edge team.