Senior Analog IC Design Lead - Clocking & High-Speed PHY

Micron Technology; Boise (ID); On-site; USD 140,000 - 210,000; Full time

Job summary

Micron Technology in Boise seeks a Principal Analog Design Engineer to lead custom clocking and SerDes-like blocks from spec to post-silicon validation. You will own PLL/DLL/CDR architectures and work across the analog/digital boundary with the layout team on interface definitions.

Responsibilities include transistor-level simulation, corner and jitter analysis, and developing robust testbenches. AI/ML tooling experience is a plus and collaboration across the Interface Pathfinding team is

Qualifications

• 10+ years of analog/mixed-signal IC build experience with at least one tape-out.
• Deep expertise in clocking circuit design (PLL/DLL/CDR) and CMOS implementation.
• Strong transistor-level simulation and yield analysis experience.
• Ability to use AI/ML tools to improve productivity and design insight.

Responsibilities

• Lead development of clocking and transmitter/receiver analog blocks.
• Contribute to PHY architecture decisions and interface specs with digital blocks.
• Build transistor-level testbenches; evaluate process corners and yield sensitivity.
• Collaborate with layout and guide post-silicon characterization.

Skills

Analog IC design

Clocking circuits

Transistor-level SPICE

Monte Carlo / jitter analysis

AI/ML productivity

Education

Electrical Engineering degree (BS/MS/PhD)

Tools

HSpice

CMOS design tools

Job description

Micron Technology in Boise seeks a Principal Analog Design Engineer to lead custom clocking and SerDes-like blocks from spec to post-silicon validation. You will own PLL/DLL/CDR architectures and work across the analog/digital boundary with the layout team on interface definitions.

Responsibilities include transistor-level simulation, corner and jitter analysis, and developing robust testbenches. AI/ML tooling experience is a plus and collaboration across the Interface Pathfinding team is