Principal Analog Design Engineer — Mixed-Signal PHY (Clocking / High-Speed I/O)

Micron Technology; Boise (ID); On-site; USD 140,000 - 210,000; Full time

Job summary

Micron Technology in Boise seeks a Principal Analog Design Engineer to lead custom clocking and SerDes-like blocks from spec to post-silicon validation. You will own PLL/DLL/CDR architectures and work across the analog/digital boundary with the layout team on interface definitions.

Responsibilities include transistor-level simulation, corner and jitter analysis, and developing robust testbenches. AI/ML tooling experience is a plus and collaboration across the Interface Pathfinding team is

Qualifications

• 10+ years of analog/mixed-signal IC build experience with at least one tape-out.
• Deep expertise in clocking circuit design (PLL/DLL/CDR) and CMOS implementation.
• Strong transistor-level simulation and yield analysis experience.
• Ability to use AI/ML tools to improve productivity and design insight.

Responsibilities

• Lead development of clocking and transmitter/receiver analog blocks.
• Contribute to PHY architecture decisions and interface specs with digital blocks.
• Build transistor-level testbenches; evaluate process corners and yield sensitivity.
• Collaborate with layout and guide post-silicon characterization.

Skills

Analog IC design

Clocking circuits

Transistor-level SPICE

Monte Carlo / jitter analysis

AI/ML productivity

Education

Electrical Engineering degree (BS/MS/PhD)

Tools

HSpice

CMOS design tools

Job description

Our vision is to transform how the world uses information to enrich life for all.

Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.

Micron’s Interface Pathfinding team builds and validates innovative PHY solutions for high-speed chip-to-chip and memory interconnect. Our focus is on pushing the boundaries of what is possible in high-speed signaling and validating those boundaries with real hardware data.

As a Principal Analog Design Engineer, you will be at the forefront of developing custom and original analog circuits. This is not integration or maintenance work, but an ambitious opportunity to contribute to world-class clocking, transmitter, and receiver circuits. You will own the complete lifecycle of building, from specifications through to post-silicon characterization.

Responsibilities

• Lead the development of specialized analog components, focusing primarily on clocking (PLL, DLL, CDR) and transmitter/receiver circuits.
• Contribute to the top-level PHY analog architecture decisions, including clocking topology and signal chain partitioning.
• Build and maintain transistor-level simulation testbenches; perform process corner, statistical sampling, and evaluate variations to characterize build margin and yield sensitivity.
• Define and detail clear interface specifications between custom analog blocks and the digital control wrapper.
• Collaborate closely with the layout team to guide custom analog layout and support post-silicon characterization in the lab.

Minimum Qualifications

• BS, MS, or PhD in Electrical Engineering or related field, or equivalent experience.
• 10+ years of analog/mixed-signal IC build experience with at least one tape-out in a primary circuit ownership role.
• Deep expertise in clocking circuit building — PLL, DLL, or CDR architecture and transistor-level implementation in sophisticated CMOS nodes.
• Strong transistor-level simulation skills using HSpice or equivalent; comfort with corner, Monte Carlo, and mismatch analysis for yield-aware development.
• Proven understanding of jitter analysis and its impact on high-speed link timing margins.
• Ability to use AI/ML/LLMs for productivity and efficiency

Preferred Qualifications

• Experience with high-speed transmitter development — output driver architectures, pre-emphasis, swing control, and impedance matching for multi-Gbps die-to-die or SerDes interfaces.
• Background in rapid receiver development — sense amplifiers, CTLE/DFE equalization, sampler development, and threshold calibration.
• Familiarity with die-to-die or chip-to-chip PHY architectures — UCIe, AIB, BoW, or proprietary short-reach interconnect standards.
• Experience working with OTP/fuse-based calibration architectures and analog trim loop implementation.
• Post-silicon characterization experience — correlating simulation results to measured eye diagrams, BER curves, phase noise plots, and jitter histograms on real hardware.

As a world leader in the semiconductor industry, Micron is dedicated to your personal wellbeing and professional growth. Micron benefits are designed to help you stay well, provide peace of mind and help you prepare for the future. We offer a choice of medical, dental and vision plans in all locations enabling team members to select the plans that best meet their family healthcare needs and budget. Micron also provides benefit programs that help protect your income if you are unable to work due to illness or injury, and paid family leave. Additionally, Micron benefits include a robust paid time‑off program and paid holidays. For additional information regarding the Benefit programs available, please see the Benefits Guide posted on micron.com/careers/benefits.

Micron is proud to be an equal opportunity workplace and is an affirmative action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, age, national origin, citizenship status, disability, protected veteran status, gender identity or any other factor protected by applicable federal, state, or local laws.

Micron Prohibits the use of child labor and complies with all applicable laws, rules, regulations, and other international and industry labor standards.

Micron does not charge candidates any recruitment fees or unlawfully collect any other payment from candidates as consideration for their employment with Micron.