Senior Analog Engineer: High-Speed DDR I/O & PLL

Renesas; Duluth (GA); On-site; USD 140,000 - 190,000; Full time

Benefits offered by this job

Competitive benefits package

Job summary

Renesas is seeking an Architect to design and verify CMOS analog blocks for custom ASICs, focusing on DDR I/O interfaces (Rx, Tx, PLL) with stringent performance, area, and power constraints. You will collaborate with digital teams to ensure seamless integration and robust design verification.

The role requires an advanced degree in Electronics/Microelectronics, 5–8 years of analog design experience, and strong proficiency in Cadence tools.

Qualifications

• Advanced degree in Electronics/Microelectronics Engineering or related discipline.
• 5-8 years of analog circuit design experience (3-6 years with Ph.D.).
• Deep understanding of high-speed DDR I/O interface design and optimization.
• Proficiency with analog design tools and simulation techniques (Cadence Virtuoso, Maestro, Spectre, HSPICE).
• Strong understanding of signal integrity and analog design principles.
• Excellent verbal and written communication in English.

Responsibilities

• Design, simulate, and verify CMOS analog blocks for DDR I/O interfaces (Rx, Tx, PLL) in custom ASICs.
• Optimize analog circuits for performance, area, and power under tight timelines.
• Collaborate with digital design, systems engineers, and other stakeholders.
• Prepare design specifications, reports, and verification documentation.
• Stay current with industry trends and introduce low-power design improvements.
• Ensure layouts meet analog matching and performance standards.

Skills

High-speed DDR I/O design

Analog circuit design

Cadence tool proficiency

Signal integrity

English communication

Education

Advanced degree in Electronics/Microelectronics Engineering

PhD preferred

Tools

Cadence Virtuoso

Maestro

Spectre

HSPICE

Job description

Renesas is seeking an Architect to design and verify CMOS analog blocks for custom ASICs, focusing on DDR I/O interfaces (Rx, Tx, PLL) with stringent performance, area, and power constraints. You will collaborate with digital teams to ensure seamless integration and robust design verification.

The role requires an advanced degree in Electronics/Microelectronics, 5–8 years of analog design experience, and strong proficiency in Cadence tools.