Senior AI-Driven Power Integrity Co-Design Architect

NVIDIA Corporation; Santa Clara (CA); Hybrid; USD 136,000 - 219,000; Full time

Job summary

NVIDIA Corporation is seeking a Senior Power Integrity Co-Design Engineer in California to architect and deliver di/dt mitigation across silicon, package, board, and platform. You will translate noise targets into shipped specifications and feed silicon findings into the next generation's build.

This role requires strong systems thinking, the ability to navigate ambiguity, and hands-on bench work with scopes, probes, and DAQ, plus simulator-driven verification.

Qualifications

• BS / MS / PhD in EE, CE, or related (or equivalent experience).
• 5+ years in silicon power integrity, voltage noise, or PDN.
• Deep expertise in at least one of: di/dt analysis and mitigation, voltage droop, PDN design (die + package + board), transient noise, decap budgeting, voltage regulator response.
• Hands-on silicon experience: bringup, characterization, correlation.
• You're comfortable on a bench with scopes, probes, DAQ — and in front of a simulator.
• Strong Sim-to-Si correlation instincts — the field of figuring out which side of the equals sign is wrong.

Responsibilities

• Architect voltage-noise mitigation across the full stack — silicon, package, board, platform — and own the codesign trade-offs between them.
• Co-design noise features with Speed, Power, Reliability, Circuit Design , Power-Arch, ASIC, and platform teams.
• You're the connective tissue across the codesign web.
• Work with other team members to define product-level voltage noise targets, drive them to closure, and sign them off at shipment.
• Build and take ownership of the Sim-to-Si correlation methodology for noise.
• You know when a model is lying and when silicon is.
• Model and prototype next-gen noise features — transient sense, droop response, mitigation IP, and codify them so every future program inherits them.
• Lead show-stopper noise bugs during bringup.
• The critical issues stop with you.
• Drive architecture-level codesign tradeoffs across V/F <-> Power <-> Noise <-> Reliability <-> Thermal (Noise-Variation) and (Noise-to-Closure) boundary work, where the highest-leverage innovation lives.

Skills

di/dt analysis

voltage noise

PDN design

transient noise

silicon experience

Education

BS/MS/PhD in EE or CE

Tools

Scopes

Probes

DAQ

Simulator

Job description

NVIDIA Corporation is seeking a Senior Power Integrity Co-Design Engineer in California to architect and deliver di/dt mitigation across silicon, package, board, and platform. You will translate noise targets into shipped specifications and feed silicon findings into the next generation's build.

This role requires strong systems thinking, the ability to navigate ambiguity, and hands-on bench work with scopes, probes, and DAQ, plus simulator-driven verification.