Senior AI Deployment Architect for Chip Design

Cadence

Cary (NC)

On-site

USD 180,000 - 280,000

Full time

14 days+

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Job summary

Cadence is seeking a Principal AI Forward Deployment Engineer to embed with strategic semiconductor customers and operationalize Cadence's AI tooling across end-to-end silicon design flows. You will lead end-to-end deployment, architect agentic workflows, and translate front-end, physical‑design, and methodology into measurable productivity gains powered by flagship LLMs and Cadence AI tooling.

You will be the trusted technical lead at the customer, turning AI-for-chip-design into deployed,

Qualifications

BS/MS/PhD in EE, ECE, CS, or related discipline.
10+ years of hands‑on semiconductor / chip design experience across front‑end, PD, CAD/methodology, or tape‑outs.
Fluency with industry EDA flows and pain points; shipped silicon experience.
Experience applying LLMs/AI tools to engineering work (agent-based debugging, code/RTL generation, copilots).
Excellent customer-facing communication across senior technical roles.

Responsibilities

Lead end‑to‑end deployment of Cadence AI/LLM-powered solutions into customer silicon design flows.
Architect and tune agentic workflows, prompt strategies, and RAG pipelines for EDA tasks.
Map customer methodology onto Cadence AI building blocks and identify ROI insertion points.
Define and report KPIs: cycle-time reduction, engineer-hours saved, first-pass success.
Be the senior technical face to customer teams, run design reviews and roadmaps.
Guide secure LLM access patterns and IT/Sec considerations as needed.
Capture playbooks and mentor field teams to scale deployments.