Advanced Packaging Integration and Simulation Intern

Intel Corporation; Chandler (AZ); Hybrid; USD 121,000 - 122,000; Full time

Job summary

Intel Technology Research is seeking an Advanced Packaging Integration and Simulation Intern to collaborate with researchers and engineers on next-generation package architectures, including 2.5D/3D integration and wafer-level assembly. You will develop DOE plans, build and validate simulation models, and analyze data to drive yield and reliability improvements.

The role offers hands-on experience in packaging integration, process flow definition, and data-driven engineering, with exposure to

Qualifications

• Candidate must be pursuing a PhD degree in Mechanical Engineering, Materials Science and Engineering, Electrical Engineering, Physics, Manufacturing Engineering, or a closely related STEM discipline
• Must be available to work full-time for the duration of a 3-month internship.
• 3+ months of academic or professional experience in lab experiments, engineering data analysis, or simulation/modeling workflows.
• Experience in process integration or hands-on module development.
• Programming or data analysis experience using Python, MATLAB, JMP, R, or similar tools.
• Statistical analysis, DOE, or machine learning for engineering applications.

Responsibilities

• Support advanced packaging integration activities across wafer-level and package-level process flows, including wafer level process, 2.5D/3D integration, chiplet integration, and hybrid bonding-related modules.
• Develop and execute Design of Experiments (DOE) to understand relationships among package architecture, process conditions, material behavior, and electrical/mechanical performance.
• Build, calibrate, and apply simulation models to understand mechanical characteristics of packages, interconnect quality, thermal performance, etc.
• Conduct thermo-mechanical simulations to evaluate material responses to temperature, stress, and package-level loading conditions.
• Analyze inspection, process, and simulation data to identify root causes of integration challenges and recommend improvement paths.
• Collaborate with cross-functional teams to optimize process flows for yield, reliability, manufacturability, and package performance.
• Present findings through technical presentations and potential publications.

Skills

Python

MATLAB

JMP

R

DOE

Data Analysis

Machine Learning for Engineering

Education

PhD in Mechanical Engineering

PhD in Materials Science & Engineering

PhD in Electrical Engineering

Tools

JMP

MATLAB

Python

Finite Element Analysis (FEA)

Job description

Job Details: Job Description

Intel Technology Research is advancing the future of AI and high-performance computing through innovative advanced packaging technologies and 3D heterogeneous integration. Enabling novel system architecture, developing innovating process integration and establishing predictive physics-based simulation capabilities are critical for enabling complex large form factor packages with high-bandwidth interconnect. As an Advanced Packaging Integration and Simulation Intern, you will collaborate with leading researchers, process engineers, and modeling experts to develop and assess next-generation package architectures. In this role, you will contribute to advanced Research and Dev across package integration, process flow definition and development, package modeling, yield and reliability assessment, and data analytics.

Key Responsibilities

• Support advanced packaging integration activities across wafer-level and package-level process flows, including wafer level process, 2.5D/3D integration, chiplet integration, and hybrid bonding-related modules.
• Develop and execute Design of Experiments (DOE) to understand relationships among package architecture, process conditions, material behavior, and electrical/mechanical performance.
• Build, calibrate, and apply simulation models to understand mechanical characteristics of packages, interconnect quality, thermal performance, etc.
• Conduct thermo-mechanical simulations to evaluate material responses to temperature, stress, and package-level loading conditions.
• Analyze inspection, process, and simulation data to identify root causes of integration challenges and recommend improvement paths.
• Collaborate with cross-functional teams to optimize process flows for yield, reliability, manufacturability, and package performance.
• Present findings through technical presentations and potential publications.

What You Will Gain

• Gain hands-on exposure to advanced packaging integration challenges that enable future semiconductor technologies.
• Learn how process integration, material selection, design rules, metrology, and package architecture interact to drive yield and reliability.
• Develop practical experience with developing package simulation, model validation, and data-driven engineering analysis.
• Gain exposure to advanced packaging architectures, including chiplets, 2.5D/3D integration, wafer-level assembly, and industrial leading interconnect technologies.
• Participate in technical reviews, technology forums, and intern research presentations with experienced engineers and researchers.

Minimum Qualifications

• Candidate must be pursuing a PhD degree in Mechanical Engineering, Materials Science and Engineering, Electrical Engineering, Physics, Manufacturing Engineering, or a closely related STEM discipline
• Must be available to work full-time for the duration of a 3-month internship.
• 3+ months of academic or professional experience in one or more of the following areas: Experience with laboratory experimentation, engineering data analysis, or simulation/modeling workflows.
• Experience in process integration or hands-on module development.
• Programming or data analysis experience using Python, MATLAB, JMP, R, or similar tools.
• Statistical analysis, DOE, or machine learning for engineering applications.

Preferred Qualifications

• 6+ months of academic or professional experience in one or more of the following areas: Advanced packaging, heterogeneous integration, wafer-level packaging, chiplet integration, or package assembly process development.
• Thermal/mechanical/electrical modeling, finite element analysis preferred.
• Failure analysis for semiconductor process and package assembly.

Job Type

Student / Intern

Shift

Shift 1 (United States of America)

Primary Location

US, Arizona, Phoenix

Additional Locations

US, Oregon, Hillsboro

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation or any other characteristic protected by local law, regulation, or ordinance.

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.

Annual Salary Range for jobs which could be performed in the US

$120,898.00-120,902.00 USD

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on‑site at their assigned Intel site and off‑site. * Job posting details (such as work model, location or time type) are subject to change.

ADDITIONAL INFORMATION

Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter. Intel’s official careers website.

Join us at Intel to contribute to technological advancements while building a rewarding and impactful career. Your recruiter can share more about the specific compensation range for your preferred location and job role during the hiring process.