Quantum NCG 3DHI Engineer

Jobtailor; Essex Junction (VT); On-site; USD 70,000 - 110,000; Full time

Job summary

Jobtailor is seeking a technically versatile engineer to lead 3D heterogeneous integration process development with internal teams and external suppliers. You will help advance wafer-level and die-level integration, applying deep knowledge of packaging processes and materials to improve yields and reduce cycle times.

The role requires strong communication, leadership, and project management skills, plus a willingness to travel up to 10% and a PhD is preferred.

Qualifications

• Bachelor’s or Master’s in Electrical, Mechanical, Chemical Engineering, Materials Science or related field.
• Internship or co-op experience.
• Overall GPA of at least 3.0 and good academic standing.
• English fluency, written and verbal.
• Willingness to travel up to 10%.
• Fundamental knowledge of semiconductor packaging processes and integration.
• PhD education level preferred.
• Demonstrated leadership in workplace, school projects or competitions.
• Project management skills with ability to innovate and execute.
• Ability to navigate ambiguity.
• Strong written and verbal communication skills.
• Strong planning and organizational skills.

Responsibilities

• Drive 3D heterogeneous integration process development with engineers and suppliers.
• Collaborate with OSATs to develop wafer- and die-level 2.5D and 3D integration processes.
• Develop expertise in processes, materials and tooling using characterization resources.
• Drive failure mode analysis to improve yields and reduce cycle time and costs.
• Generate IP related to wafer integration and packaging technology.
• Collaborate with teams on assignments as needed.
• Perform activities safely and support EHSS requirements.
• Perform other duties as assigned by the manager.

Skills

Project management

Leadership

Communication

Planning

Navigate ambiguity

Education

Bachelor’s degree in EE/ME/CEM/Materials Science

Master’s degree in EE/ME/CEM/Materials Science

PhD preferred

GPA of at least 3.0

Job description

• Drive 3D heterogeneous integration process development efforts and planning with unit process engineers and tools and materials suppliers
• Collaborate with OSATs to develop wafer-level and die-level 2.5D and 3D heterogeneous integration processes
• Develop expertise in processes, materials and tooling using available characterization resources
• Drive mechanistic understanding of failure modes
• Develop integration schemes to improve yields and reduce cycle time and costs
• Generate IP related to novel wafer integration and packaging technology
• Collaborate with other teams on assignments as needed
• Perform activities safely and responsibly and support Environmental, Health, Safety & Security requirements and programs
• Perform other duties assigned by the manager

Requirements

• Bachelor's or Master's in Electrical Engineering, Mechanical Engineering, Chemical Engineering, Materials Science or related field from an accredited degree program
• Prior related internship or co-op experience
• Overall GPA of at least 3.0 and proven good academic standing
• English fluency, written and verbal
• Willingness to travel up to 10%
• Fundamental knowledge of semiconductor packaging process modules and integration
• PhD education level preferred
• Demonstrated prior leadership experience in workplace, school projects, competitions, etc.
• Project management skills and ability to innovate and execute solutions
• Ability to navigate ambiguity
• Strong written and verbal communication skills
• Strong planning and organizational skills

Core Competencies

Demonstrates expertise in 3D heterogeneous integration processes, semiconductor packaging, and project management while ensuring compliance with Environmental, Health, Safety & Security standards. Strong communication and organizational skills support effective collaboration and innovation in process development.

Highest-signal resume keywords

• 3D Heterogeneous Integration
• Semiconductor Packaging Process
• Project Management
• Leadership Experience
• English Fluency

Hard Skills

• Electrical Engineering
• Mechanical Engineering
• Chemical Engineering
• Materials Science
• Wafer-Level Integration
• Die-Level Integration
• Characterization Resources
• Integration Schemes
• Failure Mode Analysis
• GPA of At Least 3.0

Soft Skills

• Strong Written Communication
• Strong Verbal Communication
• Planning Skills
• Organizational Skills
• Ability to Navigate Ambiguity

Industry Keywords

• Environmental Health Safety
• Integration Processes
• Cycle Time Reduction
• Cost Reduction
• IP Generation