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Benefits offered by this job
Health Insurance
Paid Time Off
Retirement and Savings
Job summary
Arcfield is seeking a Design Lead in New York, NY, to manage ASIC design projects for advanced applications. The candidate will lead a team of engineers and is responsible for VHDL designs targeting Xilinx FPGAs. Candidates must have a relevant engineering degree and extensive experience (12-15 years) in the field, along with obtaining a Secret clearance. The compensation range is between $130,611.87 and $239,061.79, with benefits including health insurance and retirement plans.
Qualifications
12-15 years' experience with a Bachelor’s or 10-13 years with a Master’s.
Must obtain and maintain a Secret clearance.
Minimum 3 years experience in targeting VHDL designs to Xilinx FPGAs.
Minimum 5 years experience developing in VHDL and Verilog.
Responsibilities
Design, research, and develop applications for secure processing projects.
Lead ASIC design engineers and create design documents.
Verify chip functionality using HDL simulator and synthesis tools.
Supervise technical procedures and coordinate with research engineers.
Skills
VHDL design targeting Xilinx FPGAs
Cadence Virtuoso
ModelSim/QuestaSim
VHDL/Verilog/System Verilog
Education
Bachelor's degree in Hardware or Electrical Engineering
Master's degree in Hardware or Electrical Engineering
Ph.D in Hardware or Electrical Engineering
Job description
Arcfield is seeking a Design Lead in New York, NY, to manage ASIC design projects for advanced applications. The candidate will lead a team of engineers and is responsible for VHDL designs targeting Xilinx FPGAs. Candidates must have a relevant engineering degree and extensive experience (12-15 years) in the field, along with obtaining a Secret clearance. The compensation range is between $130,611.87 and $239,061.79, with benefits including health insurance and retirement plans.