ASIC Design Engineer III

Arcfield; Forest Home (NY); On-site; USD 82,437 - 198,097; Full time

Job summary

Arcfield in New York seeks an experienced ASIC Design Engineer to join a team focused on HDL-based chip design, verification and prototyping.

You will develop VHDL/Verilog, verify with ModelSim/QuestaSim, synthesize with Synopsys/Genus and port RTL to FPGA prototypes, ensuring timing, power and DFT coverage. A Secret clearance is required or can be obtained.

Qualifications

• Bachelor's (or equivalent) with 5-7 years of experience or Master’s with 3-5 years or PhD with 0-2 years.
• Must obtain and maintain a Secret clearance.
• Minimum 3 years experience targeting VHDL designs to Xilinx FPGAs.
• Minimum 3 years experience using Cadence Virtuoso.
• Minimum 5 years experience developing in VHDL and Verilog (or SystemVerilog).
• Minimum 3 years experience using ModelSim/QuestaSim.

Responsibilities

• Asic design engineer to define chip features, performance and components.
• Develop, enhance and debug VHDL/Verilog for the chip.
• Verify design with HDL simulators (ModelSim/Xcelium) and synthesize with Synopsys/Genus.
• Perform CDC/RDC verification and add DFT, memory BIST and JTAG logic.
• Port RTL to FPGA prototyping board and perform CTS and clock tree synthesis.
• Run place-and-route, static timing and power analyses after CTS.
• Package and evaluate boards; maintain technical docs and procedures.

Skills

HDL design

VHDL/Verilog

RTL development

Debugging

CDC/RDC knowledge

Team collaboration

Education

Bachelor's degree in Electrical Engineering or related field

Master's degree (preferred)

PhD (considered)

Tools

Xilinx FPGA tooling

Cadence Virtuoso

ModelSim/QuestaSim

Synopsys Genus

Xcelium

Job description

Responsibilities

• The successful candidate should be at the Career level with a complete understanding and wide application of technical principles, theories and concepts.
• Working under only general direction, provides technical solutions to a wide range of difficult problems.
• As such, you will be part of a team of ASIC design engineers to create a design document that defines the chip's features, performance, and internal components.
• You will finish developing, enhancing, and debugging the VHDL/Verifog for the chip.
• This includes verifying the functionality of the design on an HDL simulator (such as ModelSim or Xcelium) and synthesis with Synopsys or Genus.
• You will perform clock domain crossing (CDC) & reset domain crossing (RDC) verification, Design for Test (DFT) and add specific related logic (i.e. memory BIST and JTAG scan chains) to the design.
• You will develop and port the RTL to an FPGA prototyping board.
• You will perform place and route of the netlist prior to tapeout, this includes clock tree synthesis (CTS).
• You will also run static timing analysis and power analysis after the CTS and place and route.
• Packaging and an evaluation board for the physical chip must also be performed.
• As an ASIC Design Engineer, you will develop and maintain technical procedures, documentation, and manuals and compile and analyze operational data and conduct tests to establish standards for new designs or modifications to existing equipment, systems, or processes.

Qualifications

• Bachelor's (or equivalent) with 5-7 years of experience, or a Master's with 3-5 years of experience or a PhD with 0-2 years of experience.
• Must be able to obtain and maintain a Secret clearance.
• Minimum 3 years experience with targeting VHDL designs to Xilinx FPGA's.
• Minimum 3 years experience using Cadence Virtuoso.
• Minimum 5 years experience developing in VHDL and Verilog (or System Verilog).
• Minimum 3 years experience using ModelSim/QuestaSim.

Equal Pay Act

This is the projected compensation range for this position. There are differentiating factors that can impact a final salary/hourly rate, including, but not limited to, Contract Wage Determination, relevant work experience, skills and competencies that align to the specified role, geographic location (For Remote Opportunities), education and certifications as well as Federal Government Contract Labor categories. In addition, Arcfield invests in its employees beyond just compensation. Arcfield ’s benefits offerings include, dependent upon position, Health Insurance, Life Insurance, Paid Time Off, Holiday Pay, Short Term and Long-Term Disability, Retirement and Savings, Learning and Development opportunities, wellness programs as well as other optional benefit elections. Min: $82,437.89 Max: $198,097.02

EEO Statement

We are an equal opportunity employer and federal government contractor. We do not discriminate against any employee or applicant for employment as protected by law.