ASIC Design Team Lead

Arcfield; New York (NY); Hybrid; USD 130,611 - 239,061; Full time

Benefits offered by this job

Health Insurance

Paid Time Off

Retirement and Savings

Job summary

Arcfield is seeking a Design Lead in New York, NY, to manage ASIC design projects for advanced applications. The candidate will lead a team of engineers and is responsible for VHDL designs targeting Xilinx FPGAs. Candidates must have a relevant engineering degree and extensive experience (12-15 years) in the field, along with obtaining a Secret clearance. The compensation range is between $130,611.87 and $239,061.79, with benefits including health insurance and retirement plans.

Qualifications

• 12-15 years' experience with a Bachelor’s or 10-13 years with a Master’s.
• Must obtain and maintain a Secret clearance.
• Minimum 3 years experience in targeting VHDL designs to Xilinx FPGAs.
• Minimum 5 years experience developing in VHDL and Verilog.

Responsibilities

• Design, research, and develop applications for secure processing projects.
• Lead ASIC design engineers and create design documents.
• Verify chip functionality using HDL simulator and synthesis tools.
• Supervise technical procedures and coordinate with research engineers.

Skills

VHDL design targeting Xilinx FPGAs

Cadence Virtuoso

ModelSim/QuestaSim

VHDL/Verilog/System Verilog

Education

Bachelor's degree in Hardware or Electrical Engineering

Master's degree in Hardware or Electrical Engineering

Ph.D in Hardware or Electrical Engineering

Job description

Responsibilities

• The successful candidate is a recognized expert who designs, researches, and develops highly advanced applications supporting Arcfield’s secure processing projects.
• As such, you will lead a team of ASIC design engineers to create a design document that defines the chip's features, performance, and internal components.
• You will finish developing, enhancing, and debugging the VHDL/Verifog for the chip.
• This includes verifying the functionality of the design on an HDL simulator (such as ModelSim or Xcelium) and synthesis with Synopsys or Genus.
• You will perform clock domain crossing (CDC) and reset domain crossing (RDC) verification.
• You will perform Design for Test (DFT) and add specific related logic (i.e. memory BIST and JTAG scan chains) to the design. You will develop and port the RTL to an FPGA prototyping board.
• You will perform place and route of the netlist prior to tapeout, this includes clock tree synthesis (CTS).
• You will also help the design team run static timing analysis and power analysis after the CTS and place and route. Packaging and an evaluation board for the physical chip must also be performed.
• As Design Lead you will supervise the development and maintenance of technical procedures, documentation, and manuals and lead the Design team to compile and analyze operational data and direct tests to establish standards for new designs or modifications to existing equipment, systems, or processes.
• You will also coordinate and consult with research engineers or scientists and customer representatives to resolve design problems.

Qualifications

• Bachelor degree in Hardware or Electrical Engineering (EE) with 12-15 years of experience or a Master’s degree in Hardware or Electrical Engineering (EE) with 10-13 years of experience or a Ph.D in Hardware or Electrical Engineering (EE) with 10+ years of experience.
• Must be able to obtain and maintain a Secret clearance.
• Minimum 3 years experience with targeting VHDL designs to Xilinx FPGA's.
• Minimum 3 years experience using Cadence Virtuoso.
• Minimum 5 years experience developing in VHDL and Verilog (or system Verilog).
• Minimum 3 years experience using ModelSim/QuestaSim.

Equal Pay Act

This is the projected compensation range for this position. There are differentiating factors that can impact a final salary/hourly rate, including, but not limited to, Contract Wage Determination, relevant work experience, skills and competencies that align to the specified role, geographic location (For Remote Opportunities), education and certifications as well as Federal Government Contract Labor categories. In addition, Arcfield invests in its employees beyond just compensation. Arcfield ’s benefits offerings include, dependent upon position, Health Insurance, Life Insurance, Paid Time Off, Holiday Pay, Short Term and Long-Term Disability, Retirement and Savings, Learning and Development opportunities, wellness programs as well as other optional benefit elections. Min: $130,611.87 Max: $239,061.79

EEO Statement

We are an equal opportunity employer and federal government contractor. We do not discriminate against any employee or applicant for employment as protected by law.