RTL Static Verification Engineer – Tooling & Methodology

AMD; San Jose (CA); On-site; USD 120,000 - 150,000; Full time

Job summary

AMD in San Jose is looking for an engineer to plan, develop, and maintain EDA tools focused on RTL static checks. The role involves leading the development of a static RTL quality-checking tool, working closely with various teams to integrate the tool into workflows, and supporting design flows. Candidates should have experience with SystemVerilog, scripting languages, and a degree in Electronics or Computer Engineering. Benefits are standard for AMD and equal opportunity is emphasized.

Qualifications

• Strong working knowledge of SystemVerilog and UPF.
• Demonstrated experience with RTL lint and static analysis.
• Experience debugging RTL issues.

Responsibilities

• Lead the development of a static RTL quality-checking tool.
• Collaborate with RTL, verification, and methodology teams.
• Support design flows including SystemVerilog and static analysis tools.

Skills

SystemVerilog

Static RTL checking methodologies

Static analysis tools

Scripting languages (Python, Perl, Tcl, shell)

Education

Bachelor’s or master’s degree in Electronics Engineering or Computer Engineering

Tools

Linux

Windows

Verilog

VHDL

Job description

AMD in San Jose is looking for an engineer to plan, develop, and maintain EDA tools focused on RTL static checks. The role involves leading the development of a static RTL quality-checking tool, working closely with various teams to integrate the tool into workflows, and supporting design flows. Candidates should have experience with SystemVerilog, scripting languages, and a degree in Electronics or Computer Engineering. Benefits are standard for AMD and equal opportunity is emphasized.