RTL Intern

Etched.ai, Inc.; San Jose (CA); On-site; USD 33,480 - 66,960; Full time

Benefits offered by this job

Generous housing support

Daily lunch and dinner

Direct mentorship from industry leaders

Job summary

Etched.ai, Inc. in San Jose seeks an RTL Intern to design microarchitecture and implement logic in Verilog. You will work on cutting-edge machine learning architectures and contribute through the full design cycle from discussions to synthesis.

The ideal candidate has relevant educational progress in engineering and familiarity with high-speed digital logic and ASIC design. This is a 12-week paid internship with generous housing support, mentorship, and meals provided.

Qualifications

• Progress towards a degree in electrical or computer engineering.
• Familiarity with high-speed digital logic.
• Understand ASIC or SoC design concepts.

Responsibilities

• Help design microarchitecture and implement logic in Verilog.
• Contribute to RTL block development.
• Participate in the full design cycle.

Skills

Familiarity with high-speed digital logic

Exposure to ASIC or SoC design concepts

Familiarity with SystemVerilog

Familiarity with Python

Ability to learn quickly

Education

Progress towards a Bachelor’s, Master’s, or PhD degree in electrical engineering, computer engineering

Tools

UVM

Job description

About Etched

Etched is building the world’s first AI inference system purpose‑built for transformers — delivering over 10x higher performance and dramatically lower cost and latency than a B200. With Etched ASICs, you can build products that would be impossible with GPUs, like real‑time video generation models and extremely deep & parallel chain‑of‑thought reasoning agents. Backed by hundreds of millions from top‑tier investors and staffed by leading engineers, Etched is redefining the infrastructure layer for the fastest growing industry in history.

Job Summary

As an RTL Intern at Etched, you will help design microarchitecture and implement logic in Verilog. You will work with cutting‑edge machine learning architectures, contribute to RTL block development, and participate in the full design cycle—from microarchitecture discussions to synthesis and timing feedback. You do not necessarily need prior ML/AI hardware experience; just the ability to learn quickly in a fast‑paced, high‑autonomy environment.

You may be a good fit if you have

• Progress towards a Bachelor’s, Master’s, or PhD degree in electrical engineering, computer engineering, or a related field.
• Familiarity with high‑speed digital logic
• Exposure to ASIC or SoC design concepts
• Familiarity with SystemVerilog, UVM, or Python
• Familiarity with verification work and writing test benches
• Familiarity with physical design flows and tooling
• Are able to learn quickly about transformers and other aspects of modern artificial intelligence

Strong candidates may also have experience with

• Familiarity with transformer models and machine learning
• Familiarity with numerical representations and functions
• Familiarity with clocking and reset schemes
• Ability to program with Python or another scripting language

We encourage you to apply even if you do not believe you meet every single qualification.

Program details

• 12‑week paid internship (June - August 2026)
• Generous housing support for those relocating
• Daily lunch and dinner in our office
• Based at our office in San Jose, CA
• Direct mentorship from industry leaders and world‑class engineers
• Opportunity to work on one of the most important problems of our time

For any questions, contact [e-mail]

How we’re different

Etched believes in the Bitter Lesson. We think most of the progress in the AI field has come from using more FLOPs to train and run models, and the best way to get more FLOPs is to build model‑specific hardware. Larger and larger training runs encourage companies to consolidate around fewer model architectures, which creates a market for single‑model ASICs.

We are a fully in‑person team in San Jose (Santana Row), and greatly value engineering skills. We do not have boundaries between engineering and research, and we expect all of our technical staff to contribute to both as needed.