DV Intern

Etched; San Jose (CA); On-site; USD 123,000 - 145,000; Full time

Benefits offered by this job

Generous housing support

Daily lunch and dinner in the office

Direct mentorship from industry leaders

Mentorship

On-site San Jose

Job summary

A leading AI hardware company is seeking a Design Verification intern in San Jose, CA, for a 12-week paid internship. The role involves ensuring custom IPs for chips are high-performance and silicon-ready, requiring expertise in electrical engineering. Strong candidates will have familiarity with digital logic, ASIC design concepts, and knowledge of SystemVerilog or Python. The internship offers direct mentorship and housing support, along with meals provided during work hours.

Qualifications

• Currently pursuing a degree in electrical engineering, computer engineering, or related field.
• Understanding of digital logic and ASIC/SoC design concepts.
• Knowledge of verification work and test bench writing.
• Knowledge of SystemVerilog, UVM, or Python.
• Exposure to physical design flows and tooling.
• Willingness to learn about transformers and AI concepts.

Responsibilities

• Ensure custom IPs are robust, high-performance, and silicon-ready.
• Collaborate with architects and designers for validation.
• Validate correctness and performance across hardware-software stacks.

Skills

Familiarity with high-speed digital logic

Exposure to ASIC or SoC design concepts

Familiarity with SystemVerilog

Familiarity with UVM

Familiarity with Python

Quick learning about transformers and AI aspects

Education

Progress towards a Bachelor’s, Master’s, or PhD in Electrical Engineering or related field

Tools

SystemVerilog

UVM

Python

Job description

About Etched

Etched is building the world’s first AI inference system purpose-built for transformers - delivering over 10x higher performance and dramatically lower cost and latency than a B200. With Etched ASICs, you can build products that would be impossible with GPUs, like real-time video generation models and extremely deep & parallel chain-of-thought reasoning agents. Backed by hundreds of millions from top-tier investors and staffed by leading engineers, Etched is redefining the infrastructure layer for the fastest growing industry in history.

Job Summary

As a Design Verification intern, you will ensure the custom IPs powering our chips — including systolic arrays, DMA engines, and NoCs — are robust, high-performance, and silicon-ready. This role demands creativity, deep technical ability, and the drive to tackle complex verification challenges. You will collaborate with architects, RTL designers, and SW/FW/emulation teams to validate correctness and performance across the full hardware-software stack.

You may be a good fit if you have

• Progress towards a Bachelor’s, Master’s, or PhD degree in electrical engineering, computer engineering, or a related field.
• Familiarity with high-speed digital logic
• Exposure to ASIC or SoC design concepts
• Familiarity with SystemVerilog, UVM, or Python
• Familiarity with verification work and writing test benches
• Familiarity with physical design flows and tooling
• Are able to learn quickly about transformers and other aspects of modern artificial intelligence

Strong candidates may also have experience (Nice to have qualifications)

• Familiarity with transformer models and machine learning
• UVM or formal verification experience
• Ability to program with Python or another scripting language

We encourage you to apply even if you do not believe you meet every single qualification.

Program details

• 12-week paid internship (June - August 2026)
• Generous housing support for those relocating
• Daily lunch and dinner in our office
• Based at our office in San Jose, CA
• Direct mentorship from industry leaders and world-class engineers
• Opportunity to work on one of the most important problems of our time

For any questions, contact [e-mail]

How we’re different

Etched believes in the Bitter Lesson. We think most of the progress in the AI field has come from using more FLOPs to train and run models, and the best way to get more FLOPs is to build model-specific hardware. Larger and larger training runs encourage companies to consolidate around fewer model architectures, which creates a market for single-model ASICs.

We are a fully in-person team in San Jose (Santana Row), and greatly value engineering skills. We do not have boundaries between engineering and research, and we expect all of our technical staff to contribute to both as needed.