PD Intern

Etched.ai, Inc.; San Jose (CA); On-site; USD 34,440 - 55,104; Full time

Benefits offered by this job

12-week paid internship

Generous housing support

Daily lunch and dinner in the office

Job summary

Etched.ai, Inc. is hiring a Physical Design intern in San Jose, California. The intern will work on realizing front-end designs in silicon and assist in automating Physical Design flows to improve speed to final signoff.

Qualified candidates should be working towards a relevant degree in electrical or computer engineering and have a familiarity with digital logic, ASIC design concepts, and relevant programming languages. The internship includes housing support and daily meals.

Qualifications

• Progress towards a relevant degree in electrical engineering or computer engineering.
• Familiarity with high-speed digital logic.
• Familiarity with physical design flows and tooling.

Responsibilities

• Realize front-end designs in silicon to improve iteration speed.
• Develop and run Physical Design flows to synthesize blocks.
• Advise on RTL design decisions.

Skills

High-speed digital logic

ASIC or SoC design concepts

SystemVerilog

UVM

Python

Verification work

Physical design flows

Education

Progress towards a Bachelor’s, Master’s, or PhD in electrical/computer engineering

Job description

About Etched

Etched is building the world’s first AI inference system purpose-built for transformers - delivering over 10x higher performance and dramatically lower cost and latency than a B200. With Etched ASICs, you can build products that would be impossible with GPUs, like real-time video generation models and extremely deep & parallel chain-of-thought reasoning agents. Backed by hundreds of millions from top-tier investors and staffed by leading engineers, Etched is redefining the infrastructure layer for the fastest growing industry in history.

Job Summary

As a Physical Design intern for Etched, you will be responsible for realizing our front-end designs in silicon, helping Etched to improve iteration speed to final signoff. You will assist in developing and running Physical Design flows to synthesize blocks, automate final design checks, and advise RTL design decisions. We are looking for Fall '26, Spring '27, and Summer '27 interns.

You may be a good fit if you have

• Progress towards a Bachelor’s, Master’s, or PhD degree in electrical engineering, computer engineering, or a related field.
• Familiarity with high-speed digital logic
• Exposure to ASIC or SoC design concepts
• Familiarity with SystemVerilog, UVM, or Python
• Familiarity with verification work and writing test benches
• Familiarity with physical design flows and tooling
• Are able to learn quickly about transformers and other aspects of modern artificial intelligence

Strong candidates may also have experience with

• Familiarity with transformer models and machine learning
• Familiarity with numerical representations and functions (RTL)
• Familiarity with clocking and reset schemes (RTL/PD)
• UVM or formal verification experience (DV)
• Ability to program with Python or another scripting language

We encourage you to apply even if you do not believe you meet every single qualification.

Program details

• 12-week paid internship
• Generous housing support for those relocating
• Daily lunch and dinner in our office
• Based at our office in San Jose, CA
• Direct mentorship from industry leaders and world-class engineers
• Opportunity to work on one of the most important problems of our time

How we’re different

Etched believes in the Bitter Lesson. We think most of the progress in the AI field has come from using more FLOPs to train and run models, and the best way to get more FLOPs is to build model-specific hardware. Larger and larger training runs encourage companies to consolidate around fewer model architectures, which creates a market for single-model ASICs.

We are a fully in-person team in San Jose (Santana Row), and greatly value engineering skills. We do not have boundaries between engineering and research, and we expect all of our technical staff to contribute to both as needed.