RTL Intern

The Consensus; San Jose (CA); On-site; USD 22,320 - 35,712; Full time

Benefits offered by this job

Housing support

Lunch and dinner in office

Mentorship from leaders

Paid internship

Job summary

Etched is seeking an RTL Intern to help design microarchitecture and implement logic in Verilog. You’ll work with cutting-edge ML architectures, contribute to RTL block development, and participate in the full design cycle—from microarchitecture discussions to synthesis and timing feedback.

We welcome candidates who can learn quickly in a fast-paced, high-autonomy environment. This is a 12-week paid internship based at our San Jose, CA office, with direct mentorship from industry leaders and

Qualifications

• Progress towards a Bachelor’s, Master’s, or PhD degree in electrical or computer engineering or a related field.
• Familiarity with high-speed digital logic and ASIC/SoC concepts.
• Exposure to SystemVerilog, UVM, or Python; test benches familiarity.
• Ability to learn quickly in a fast-paced, high-autonomy environment.

Responsibilities

• Assist in RTL microarchitecture discussions and verilog implementation.
• Contribute to RTL block development and participate in synthesis and timing feedback.
• Collaborate across teams in the full design cycle throughout the internship.

Skills

RTL design

SystemVerilog

UVM

Python

High-speed digital logic

ASIC/SoC concepts

Learning ability

Verilog

Education

Electrical engineering / Computer engineering / related field (Bachelor/Master/PhD)

Tools

SystemVerilog

UVM

Python

Job description

About Etched

Etched is building hardware for frontier intelligence. We co-design chips, racks, software, and manufacturing to deliver best-in-class throughput and latency across both prefill and decode workloads. Our first products are heavily focused on inference. Backed by hundreds of millions from top-tier investors and staffed by leading engineers, Etched is redefining the infrastructure layer for the fastest growing industry in history.

Job Summary

As an RTL Intern at Etched, you will help design microarchitecture and implement logic in verilog. You will work with cutting-edge machine learning architectures, contribute to RTL block development, and participate in the full design cycle—from microarchitecture discussions to synthesis and timing feedback. You do not necessarily need prior ML/AI hardware experience; just the ability to learn quickly in a fast-paced, high-autonomy environment. We are looking for Fall '26, Spring '27, and Summer '27 interns.

You may be a good fit if you have

• Progress towards a Bachelor’s, Master’s, or PhD degree in electrical engineering, computer engineering, or a related field.
• Familiarity with high-speed digital logic
• Exposure to ASIC or SoC design concepts
• Familiarity with SystemVerilog, UVM, or Python
• Familiarity with verification work and writing test benches
• Familiarity with physical design flows and tooling
• Are able to learn quickly about transformers and other aspects of modern artificial intelligence

Strong candidates may also have experience with

• Familiarity with modern ML and LLM model architectures
• Familiarity with numerical representations and functions
• Familiarity with clocking and reset schemes
• Ability to program with Python or another scripting language

We encourage you to apply even if you do not believe you meet every single qualification.

Program details

• 12-week paid internship
• Generous housing support for those relocating
• Daily lunch and dinner in our office
• Based at our office in San Jose, CA
• Direct mentorship from industry leaders and world-class engineers
• Opportunity to work on one of the most important problems of our time

For any questions, contact [e-mail]

How we’re different

Etched believes in the Bitter Lesson. We are the first inference-focused frontier AI system, betting early on transformer and transformer-like architectures and on increasing model sizes. Our addressable market is the entirety of inference, unlike many of our competitors.

We are a fully in-person team in San Jose (Santana Row), and greatly value engineering skills. We do not have boundaries between engineering and research, and we expect all of our technical staff to contribute to both and work across disciplines as needed.