RTL IC Design Engineer – Onsite, Bonus & RSUs, Relocation

Insight Global; Colorado Springs (CO); On-site; USD 110,000 - 170,000; Full time

Benefits offered by this job

Relocation

RSUs on signing

401(k) matching

Benefits package

Holidays

Sick leave

Vacation time

Job summary

Insight Global is seeking RTL IC Design Engineers to join a leading semiconductor company in Colorado Springs, CO or San Jose. The role focuses on Verilog/SystemVerilog RTL design for PCIe Switch and enterprise storage products, with onsite, regular hours Monday–Friday.

You will collaborate with Verification, Software/Firmware, Emulation, and Validation teams, drive timing closure, and contribute to megadatacenter scale designs. Relocation offered.

Qualifications

• Bachelor's degree in Electrical Engineering, Electronics Engineering, Computer Science, or Computer Engineering.
• 3-12 years' experience in RTL/digital design.
• Strong Verilog/SystemVerilog coding for RTL.
• Understanding of Clock Domain Crossing and Reset Domain Crossing.
• Strong written and verbal communication.

Responsibilities

• High-level architecture specification analysis and review.
• Micro-architecture development and documentation.
• Verilog/SystemVerilog RTL implementation for RTL designs.
• RTL optimization for timing closure across multiple domains.
• Robust RTL debugging and cross-functional collaboration.
• Support RTL issues with Verification, Software/Firmware, Emulation, and Validation teams.
• Lab support for silicon during validation.

Skills

RTL / Digital design

Verilog / SystemVerilog

Clock Domain Crossing

Communication skills

Team collaboration

Education

Bachelor's degree (EE/CS)

Job description

Insight Global is seeking RTL IC Design Engineers to join a leading semiconductor company in Colorado Springs, CO or San Jose. The role focuses on Verilog/SystemVerilog RTL design for PCIe Switch and enterprise storage products, with onsite, regular hours Monday–Friday.

You will collaborate with Verification, Software/Firmware, Emulation, and Validation teams, drive timing closure, and contribute to megadatacenter scale designs. Relocation offered.