RTL Engineer

Sintegra Inc.; Santa Clara (CA); On-site; USD 150,000 - 230,000; Full time

Job summary

Sintegra Inc. in Santa Clara is seeking a Senior Engineer with deep expertise in Clock Domain Crossing (CDC) analysis and RTL Synthesis to drive robust signoff for complex SoCs on advanced nodes.

The role requires hands-on experience with multiple tapeouts, strong scripting skills, and the ability to manage CDC and synthesis closure from RTL through implementation, collaborating with cross‑functional teams.

Qualifications

• BS/MS in Electrical Engineering, Computer Engineering, or related field.
• 8+ years of industry experience in synthesis and CDC verification.
• Proven track record with multiple tapeouts on advanced nodes (7nm and below).

Responsibilities

• Perform CDC analysis and verification across block-level and full-chip designs.
• Develop and maintain CDC methodologies and flows to ensure robust signoff.
• Drive RTL synthesis using industry-standard tools, optimizing QoR (Power, Performance, Area).
• Collaborate with design, verification, and physical design teams to align constraints and methodology.
• Debug and resolve complex CDC and synthesis issues across large-scale SoCs.
• Contribute to methodology improvements and automation for synthesis and CDC closure.

Skills

CDC analysis

RTL synthesis

Scripting (Tcl/Python/Perl)

Debugging

Communication skills

Tapeouts

Education

BS/MS in EE or CE

Tools

Synopsys Design Compiler

Fusion Compiler

SpyGlass CDC

Conformal

Job description

We are seeking a Senior Engineer with deep expertise in Clock Domain Crossing (CDC) analysis and RTL Synthesis to join our team in Santa Clara. This role is focused on ensuring robust CDC signoff and driving synthesis flows for complex SoC designs on advanced nodes. The ideal candidate will have hands‑on experience with multiple tapeouts and the ability to independently manage CDC and synthesis closure from RTL through implementation.

Key Responsibilities

• Perform CDC analysis and verification across block‑level and full‑chip designs.
• Develop and maintain CDC methodologies and flows to ensure robust signoff.
• Drive RTL synthesis using industry‑standard tools, optimizing QoR (Power, Performance, Area).
• Collaborate with design, verification, and physical design teams to align constraints and methodology.
• Debug and resolve complex CDC and synthesis issues across large‑scale SoCs.
• Contribute to methodology improvements and automation for synthesis and CDC closure.

Required Qualifications

• BS/MS in Electrical Engineering, Computer Engineering, or related field.
• 8+ years of industry experience in synthesis and CDC verification.
• Proven track record with multiple tapeouts on advanced nodes (7nm and below).
• Hands‑on expertise with tools such as Synopsys Design Compiler/Fusion Compiler (synthesis) and SpyGlass CDC/Conformal (CDC).
• Strong scripting skills (Tcl, Python, Perl) for flow automation.
• Excellent debugging, analytical, and communication skills.

Preferred Skills

• Experience with multi-clock domain designs and complex SoC architectures.
• Familiarity with power‑aware synthesis and CDC methodologies.
• Exposure to high‑speed interfaces (PCIe, DDR, SerDes) and their CDC/timing requirements.
• Background in HPC, AI accelerators, or networking silicon.