Design for Test (DFT) Engineer

jobr.pro; Mountain View (CA); On-site; USD 300,000 - 350,000; Full time

Benefits offered by this job

Equity grant

Medical, dental, vision

401(k)

Standard PTO

Job summary

jobr.pro is seeking an experienced Design-for-Test (DFT) Engineer to join their silicon engineering team in Mountain View, California. This pivotal role involves collaborating across DFT disciplines, implementing test access architecture for advanced multi-die packages, and ensuring high-quality, testable silicon to support their cutting-edge technologies.

The ideal candidate will have extensive DFT experience, particularly with complex digital SoC/ASIC designs, and be adept at DFT flow development, as well as automation and verification processes. We offer competitive compensation and comprehensive benefits.

Qualifications

• Minimum of 7 years in DFT engineering for complex SoC/ASIC designs.
• Experience with multi-die and advanced package DFT.
• Strong command of fundamentals in DFT processes.

Responsibilities

• Advance the DFT flow including pattern generation and verification.
• Architect test access for multi-die packages.
• Perform DFT verification and silicon bring-up.

Skills

DFT engineering

Test access architecture

Scan insertion

ATPG

BIST

Boundary scan

Scripting (Tcl, Python, Perl)

Low-power DFT

Education

BS/MS in Electrical Engineering or Computer Engineering

Tools

Siemens Tessent

Verilog/SystemVerilog

Job description

About the Role

We are seeking an experienced Design-for-Test (DFT) Engineer to join our silicon engineering team and help stand up the DFT function alongside the architecture and physical-design (PD) teams. This is a ground-floor role on a leading-edge multi-die package. You will work across all aspects of the DFT discipline—from architecture and RTL insertion through pattern generation, verification, silicon bring‑up, and production test—with a particular focus on solving test access for a multi-die package from the ground up. You will partner with design, verification, physical design, and product/test engineering to help deliver high‑quality, testable, and yield‑ready silicon.

What you'll do:

• Help build out and advance the DFT flow—insertion, pattern generation, verification, and signoff—integrated into the broader RTL-to-GDSII methodology.
• Architect and implement test access for our multi-die package—post‑package scan‑chain access, known‑good‑die (KGD) sorting and screening, die‑to‑die (D2D) interconnect test, and a package‑level test‑access architecture designed in from the start rather than retrofitted.
• Implement DFT structures across the full range: scan (stuck‑at, transition/at‑speed), compression, boundary scan (JTAG/IEEE 1149.x), and IEEE 1500 core wrapping.
• Implement and verify Memory BIST, with particular emphasis on external MBIST controllers and shared/centralized BIST architectures serving distributed memory instances.
• Drive ATPG, fault simulation, coverage closure, and pattern conversion/porting to the ATE environment (STIL/WGL).
• Perform DFT verification: scan chain integrity, pattern verification, and gate‑level simulation (with SDF/timing) across all test modes.
• Help define and review DFT specifications, test access architecture, and test budgets (pin count, test time, coverage targets).
• Support silicon bring‑up, debug, diagnosis, and yield/failure analysis, correlating ATE results back to design.
• Collaborate with physical design on scan stitching, test point insertion, timing, and power‑aware test (DFT interaction with power domains/UPF).
• Document methodology and continuously automate and improve the flow.

What we're looking for

• BS/MS in Electrical Engineering, Computer Engineering, or related field.
• 7+ years of hands‑on DFT engineering on complex digital SoC/ASIC designs.
• Breadth across all of DFT — architecture, insertion, ATPG, BIST, boundary scan, verification, and silicon test — not just one sub‑domain.
• DFT flow development — building, automating, and maintaining flows, not just running them.
• Hierarchical/core‑wrapping DFT — hands‑on architecting and implementing test at the core/block level.
• Multi‑die/advanced‑package DFT — post‑package scan access, known‑good‑die (KGD) sorting, die‑to‑die interconnect test, and test‑access architecture.
• Deep Siemens Tessent expertise — Scan & ATPG (TestKompress), MemoryBIST (incl. external/shared MBIST), BoundaryScan/IJTAG (SSN a plus).
• Strong command of the fundamentals — scan insertion, ATPG (stuck‑at/transition/path‑delay), fault models, compression, JTAG/1149.x, IEEE 1500, scan‑chain architecture, and coverage analysis.
• Gate‑level simulation of test modes / DFT pattern verification; scripting for flow automation (Tcl, Python, Perl).
• Familiarity with ATE pattern formats (STIL/WGL) and the design‑to‑tester handoff; solid RTL (Verilog/SystemVerilog) and SDC.
• Low‑power DFT (UPF/CPF, power‑aware ATPG, retention/isolation test) (preferred).

Compensation

Final offers depend on level, location, and skills relevant to the role. Additional compensation: equity grant per company guidelines; medical / dental / vision; 401(k); standard PTO.

Visa Sponsorship

DensityAI sponsors qualified candidates for H-1B, O-1, TN, E-3, and other employment-based visas, and we welcome applicants on F-1 OPT and STEM-OPT. Work authorization is required at start; we provide immigration support to secure or transfer status.

Export Controls

Aspects of this role may involve access to information subject to U.S. export controls (EAR/ITAR). We may discuss licensing or scope adjustments during the interview.

Equal Opportunity

DensityAI is an Equal Opportunity Employer. We do not discriminate on the basis of race, color, religious creed, national origin, ancestry, physical or mental disability, medical condition, genetic information, marital status, sex, gender, gender identity, gender expression, age (40+), sexual orientation, military or veteran status, pregnancy, or any other status protected by law. We comply with the California CROWN Act and provide reasonable accommodations on request.

Full compensation packages are based on candidate experience and relevant certifications.

California pay range

$300,000 – $350,000 USD