Physical Design Timing Engineer

DensityAI; Mountain View (CA); On-site; USD 220,000 - 350,000; Full time

Benefits offered by this job

Equity grants

Medical, dental, vision

401(k)

Standard PTO

Job summary

DensityAI in Mountain View, California is looking for a skilled professional to own full chip and block timing methodologies for their AI accelerator silicon. The role requires extensive experience in high performance designs and the ability to work closely with chip-design and software teams.

Requirements include 10+ years in physical design, familiarity with standard PD tools, and collaboration experience. Compensation ranges from $220,000 to $350,000 USD, depending on experience.

Qualifications

• 10+ years of experience on very high performance designs at advanced technology nodes (7nm or better).
• Hands-on experience with industry-standard physical design tools.
• Ability to work closely with various teams to design complex chips.

Responsibilities

• Own Full chip and Block timing methodologies and execution to-signoff of the AI accelerator silicon.
• Develop AI-assisted tool flows to accelerate physical design timing.

Skills

Full physical design flow expertise

High performance designs experience

Industry-standard PD tools knowledge

Collaboration with architects and EDA vendors

Tools

Cadence Innovus

Synopsys Fusion Compiler

PrimeTime

Tempus

Job description

ITAR Notice

This role involves access to ITAR-controlled information. Applicants must be U.S. persons (U.S. citizens, U.S. permanent residents, asylees, or refugees) per 22 CFR 120.62.

About The Role

Own Full chip and Block timing methodologies and execution to-signoff of our AI accelerator silicon. Work with chip-design and software teams driving DensityAI's AI accelerator program from first silicon through scale-out.

Responsibilities

• Own Full chip and Block timing methodologies and execution to-signoff of our AI accelerator silicon.
• Use and develop AI-assisted tool flows to accelerate physical design timing convergence and signoff timelines.

Qualifications

• Exceptional abilities across the full physical design flow (synthesis, place & route, CTS, signoff) with emphasis on timing flows and methodologies.
• 10+ years of experience on very high performance designs at advanced technology nodes (7nm or better) and 2.5D/3D timing flows.
• Hands‑on with industry-standard PD tools (Cadence Innovus, Synopsys Fusion Compiler, or equivalent) and signoff (PrimeTime, Tempus, or equivalent).
• Demonstrated ability to work closely with architects, RTL designers, EDA vendors, and foundries to design and sign off complex chips.
• Post silicon characterization and process targeting experience is highly desirable.
• (Optional) Multi‑die packaging (CoWoS, 2.5D / 3D), thermal / IR / EM signoff, signal integrity, or DFT‑aware physical design.

Compensation

Final offers depend on level, location, and skills relevant to the role. Additional compensation: equity grant per company guidelines; medical / dental / vision; 401(k); standard PTO.

Visa Sponsorship

DensityAI sponsors qualified candidates for H-1B, O-1, TN, E-3, and other employment-based visas, and we welcome applicants on F-1 OPT and STEM-OPT. Work authorization is required at start; we provide immigration support to secure or transfer status.

Export Controls

Aspects of this role may involve access to information subject to U.S. export controls (EAR/ITAR). We may discuss licensing or scope adjustments during the interview.

Equal Opportunity Employer

DensityAI is an Equal Opportunity Employer. We do not discriminate on the basis of race, color, religious creed, national origin, ancestry, physical or mental disability, medical condition, genetic information, marital status, sex, gender, gender identity, gender expression, age (40+), sexual orientation, military or veteran status, pregnancy, or any other status protected by law. We comply with the California CROWN Act and provide reasonable accommodations on request. Full compensation packages are based on candidate experience and relevant certifications.

California Pay Range

$220,000 - $350,000 USD