RTL Design Engineer for Next-Gen ASIC/FPGA (Starlink)
SPACE EXPLORATION TECHNOLOGIES CORP
Irvine (CA)
On-site
USD 125,000 - 175,000
Full time
14 days+
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Benefits offered by this job
Comprehensive medical, vision, and dental coverage
401(k) retirement plan
3 weeks of paid vacation
10 or more paid holidays per year
Paid parental leave
Job summary
A leading aerospace company in Irvine, CA, is seeking an RTL Design Engineer to design ASICs and FPGAs for Starlink projects. The ideal candidate will collaborate with cross-disciplinary teams to create cutting-edge solutions that enhance connectivity. A Bachelor's degree in Electrical Engineering or related field and at least one year of experience in RTL design are required. This role offers competitive compensation, comprehensive benefits, and opportunities for professional growth.
Qualifications
1+ years of experience in RTL Design using SystemVerilog, Verilog or VHDL.
Team-player with a can-do attitude.
Responsibilities
Design ASICs and/or FPGAs for Starlink projects.
Participate in the full ASIC/FPGA design lifecycle.
Collaborate with cross-functional engineers in developing new technologies.
Skills
RTL Design using SystemVerilog
Experience with ASICs and FPGAs
Proficiency in Python
Ability to work in a dynamic environment
Strong foundation in electrical engineering fundamentals
Education
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or Physics
Master’s in Electrical/Computer Engineering or related field
Tools
EDA tools
Job description
A leading aerospace company in Irvine, CA, is seeking an RTL Design Engineer to design ASICs and FPGAs for Starlink projects. The ideal candidate will collaborate with cross-disciplinary teams to create cutting-edge solutions that enhance connectivity. A Bachelor's degree in Electrical Engineering or related field and at least one year of experience in RTL design are required. This role offers competitive compensation, comprehensive benefits, and opportunities for professional growth.